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authorClifford Wolf <clifford@clifford.at>2014-06-12 11:54:20 +0200
committerClifford Wolf <clifford@clifford.at>2014-06-12 11:54:20 +0200
commit482d9208aa9dacb7afe21f08c882d4881581013a (patch)
treea5a4d409f7d84cc2dc6283dcf45df3aea02cb061 /tests
parent9a6cd64fc2ca46c9aed1bd03b6898c7734420c53 (diff)
Added read_verilog -sv options, added support for bit, logic,
allways_ff, always_comb, and always_latch
Diffstat (limited to 'tests')
-rw-r--r--tests/sat/asserts.ys2
-rw-r--r--tests/sat/asserts_seq.ys2
2 files changed, 2 insertions, 2 deletions
diff --git a/tests/sat/asserts.ys b/tests/sat/asserts.ys
index de5e7c9a..d8f99492 100644
--- a/tests/sat/asserts.ys
+++ b/tests/sat/asserts.ys
@@ -1,3 +1,3 @@
-read_verilog asserts.v
+read_verilog -sv asserts.v
hierarchy; proc; opt
sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts
diff --git a/tests/sat/asserts_seq.ys b/tests/sat/asserts_seq.ys
index c622ef61..e9768664 100644
--- a/tests/sat/asserts_seq.ys
+++ b/tests/sat/asserts_seq.ys
@@ -1,4 +1,4 @@
-read_verilog asserts_seq.v
+read_verilog -sv asserts_seq.v
hierarchy; proc; opt
sat -verify -prove-asserts -tempinduct -seq 1 test_001