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authorClifford Wolf <clifford@clifford.at>2014-01-30 14:52:46 +0100
committerClifford Wolf <clifford@clifford.at>2014-01-30 15:01:28 +0100
commit4df7e03ec9eafb01e2237f307075ad8dd7b1da5a (patch)
tree197473eb2bad85ba11f6d28540c77570604cb275 /tests
parent672229eda5ba9768a0d67223a514d54dfef5534c (diff)
Bugfix in name resolution with generate blocks
Diffstat (limited to 'tests')
-rw-r--r--tests/simple/carryadd.v24
1 files changed, 24 insertions, 0 deletions
diff --git a/tests/simple/carryadd.v b/tests/simple/carryadd.v
new file mode 100644
index 00000000..4f777f79
--- /dev/null
+++ b/tests/simple/carryadd.v
@@ -0,0 +1,24 @@
+module carryadd(a, b, y);
+
+parameter WIDTH = 8;
+
+input [WIDTH-1:0] a, b;
+output [WIDTH-1:0] y;
+
+genvar i;
+generate
+ for (i = 0; i < WIDTH; i = i+1) begin:STAGE
+ wire IN1 = a[i], IN2 = b[i];
+ wire C, Y;
+ if (i == 0)
+ assign C = IN1 & IN2, Y = IN1 ^ IN2;
+ else
+ assign C = (IN1 & IN2) | ((IN1 | IN2) & STAGE[i-1].C),
+ Y = IN1 ^ IN2 ^ STAGE[i-1].C;
+ assign y[i] = Y;
+ end
+endgenerate
+
+// assert property (y == a + b);
+
+endmodule