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authorClifford Wolf <clifford@clifford.at>2014-07-17 13:49:32 +0200
committerClifford Wolf <clifford@clifford.at>2014-07-17 13:49:32 +0200
commit5867f6bcdc10cbccc196a6889f5242c0f090a2f1 (patch)
tree49d4b6f8c738d739c7fbd075b78a5cb2e30c8f87 /tests
parent6d69d4aaa81f176ec97654b5103f6f59eb98c211 (diff)
Added support for bit/part select to mem2reg rewriter
Diffstat (limited to 'tests')
-rw-r--r--tests/simple/memory.v21
1 files changed, 21 insertions, 0 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index aae3feac..21271b5e 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -134,3 +134,24 @@ always @(posedge clk) begin
end
endmodule
+
+// ----------------------------------------------------------
+
+module test06(input clk, input rst, input [2:0] idx, input [7:0] din, output [7:0] dout);
+ (* gentb_constant=0 *) wire rst;
+ reg [7:0] test [0:7];
+ integer i;
+ always @(posedge clk or posedge rst) begin
+ if (rst) begin
+ for (i=0; i<8; i=i+1)
+ test[i] <= 0;
+ end else begin
+ test[0][2] <= din[1];
+ test[0][5] <= test[0][2];
+ test[idx][3] <= din[idx];
+ test[idx][6] <= test[idx][2];
+ test[idx][idx] <= !test[idx][idx];
+ end
+ end
+ assign dout = test[idx];
+endmodule