Implemented correct handling of signed module parameters

1 files changed, 7 insertions, 1 deletions

diff --git a/tests/simple/hierarchy.v b/tests/simple/hierarchy.v
index 97612c74..17888009 100644
--- a/tests/simple/hierarchy.v
+++ b/tests/simple/hierarchy.v
@@ -4,14 +4,20 @@ module top(a, b, y1, y2, y3, y4);
 input [3:0] a;
 input signed [3:0] b;
 output [7:0] y1, y2, y3, y4;
+
+// this version triggers a bug in icarus verilog
+// submod #(-3'sd1, 3'b111 + 3'b001) foo (a, b, y1, y2, y3, y4);
+
+// this version is handled correctly by icarus verilog
 submod #(-3'sd1, -3'sd1) foo (a, b, y1, y2, y3, y4);
+
 endmodule
 
 (* gentb_skip *)
 module submod(a, b, y1, y2, y3, y4);
 parameter c = 0;
 parameter [7:0] d = 0;
-input [7:0] a, b;
+input [3:0] a, b;
 output [7:0] y1, y2, y3, y4;
 assign y1 = a;
 assign y2 = b;