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authorClifford Wolf <clifford@clifford.at>2015-04-07 20:27:10 +0200
committerClifford Wolf <clifford@clifford.at>2015-04-07 20:27:10 +0200
commit724cead61d07906bf652c2d4b0f18360b6a13a29 (patch)
tree4e717788fdcd64933ea4cb5c91ea4d700cbfbef4 /tests
parent1f33b2a490cf44ec24de5e085ff2957a680519fb (diff)
Added "pmuxtree" command
Diffstat (limited to 'tests')
-rw-r--r--tests/various/muxcover.ys51
1 files changed, 51 insertions, 0 deletions
diff --git a/tests/various/muxcover.ys b/tests/various/muxcover.ys
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+
+read_verilog -formal <<EOT
+ module gate (input [2:0] A, B, C, D, X, output reg [2:0] Y);
+ always @*
+ (* parallel_case *)
+ casez (X)
+ 3'b??1: Y = A;
+ 3'b?1?: Y = B;
+ 3'b1??: Y = C;
+ 3'b000: Y = D;
+ endcase
+ endmodule
+EOT
+
+
+## Examle usage for "pmuxtree" and "muxcover"
+
+proc
+pmuxtree
+techmap
+muxcover -mux4
+
+splitnets -ports
+clean
+# show
+
+
+## Equivalence checking
+
+read_verilog -formal <<EOT
+ module gold (input [2:0] A, B, C, D, X, output reg [2:0] Y);
+ always @*
+ casez (X)
+ 3'b001: Y = A;
+ 3'b010: Y = B;
+ 3'b100: Y = C;
+ 3'b000: Y = D;
+ default: Y = 'bx;
+ endcase
+ endmodule
+EOT
+
+proc
+splitnets -ports
+techmap -map +/simcells.v t:$_MUX4_
+
+equiv_make gold gate equiv
+hierarchy -top equiv
+equiv_simple -undef
+equiv_status -assert
+