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authorClifford Wolf <clifford@clifford.at>2013-11-24 17:30:04 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-24 17:30:04 +0100
commit7eaad2218dab9feec82e8ffe7adbc58463cadb7d (patch)
tree601f6f90387147bd98b40dcae83bf5eaa4ab650c /tests
parentf71e27dbf15d063ca45378ff2eb2d8102220f199 (diff)
Removed now obsolete test cases
Diffstat (limited to 'tests')
-rw-r--r--tests/no-icarus/README2
-rw-r--r--tests/no-icarus/autowire.v25
-rw-r--r--tests/no-icarus/var_range.v45
3 files changed, 0 insertions, 72 deletions
diff --git a/tests/no-icarus/README b/tests/no-icarus/README
deleted file mode 100644
index b43e7c02..00000000
--- a/tests/no-icarus/README
+++ /dev/null
@@ -1,2 +0,0 @@
-This directory contains test cases that can't be tested using Icarus Verilog
-because they exceed the Verilog subset that is supported by Icarus Verilog.
diff --git a/tests/no-icarus/autowire.v b/tests/no-icarus/autowire.v
deleted file mode 100644
index 3633d427..00000000
--- a/tests/no-icarus/autowire.v
+++ /dev/null
@@ -1,25 +0,0 @@
-
-module test01(a, b, y);
-
-input [3:0] a, b;
-output [3:0] y;
-
-assign temp1 = a + b;
-assign temp2 = ~temp1;
-assign y = temp2;
-
-endmodule
-
-// ------------------------------
-
-module test02(a, b, y);
-
-input [3:0] a, b;
-output [3:0] y;
-
-test01 test01_cell(A, B, Y);
-
-assign A = a, B = b, y = Y;
-
-endmodule
-
diff --git a/tests/no-icarus/var_range.v b/tests/no-icarus/var_range.v
deleted file mode 100644
index 431eacb8..00000000
--- a/tests/no-icarus/var_range.v
+++ /dev/null
@@ -1,45 +0,0 @@
-
-module test01(a, b, x, y, z);
-
-input [7:0] a;
-input [2:0] b;
-output [7:0] x, y;
-output z;
-
-assign x = a >> b;
-assign y = a[b+7:b];
-assign z = a[b];
-
-endmodule
-
-module test02(clk, a, b, x, y, z);
-
-input clk;
-input [7:0] a;
-input [2:0] b;
-output reg [7:0] x, y;
-output reg z;
-
-always @(posedge clk) begin
- x <= a >> b;
- y <= a[b+7:b];
- z <= a[b];
-end
-
-endmodule
-
-module test03(clk, a, b, x, y);
-
-input clk;
-input [2:0] a, b;
-output reg [7:0] x;
-output reg [9:0] y;
-
-always @(posedge clk)
- y[b] <= a;
-
-always @(posedge clk)
- y[b+2:b] <= a;
-
-endmodule
-