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authorClifford Wolf <clifford@clifford.at>2015-09-25 12:23:11 +0200
committerClifford Wolf <clifford@clifford.at>2015-09-25 12:23:11 +0200
commit924d9d6e86a5e9a2294479345daac1c03d78008a (patch)
tree04d28a2068b32c44c0aca2b8b815f6fc51cec427 /tests
parentec92c8965960fa814c3663e987bc2a7eb80965e5 (diff)
Added read-enable to memory model
Diffstat (limited to 'tests')
-rw-r--r--tests/techmap/mem_simple_4x1_map.v9
1 files changed, 8 insertions, 1 deletions
diff --git a/tests/techmap/mem_simple_4x1_map.v b/tests/techmap/mem_simple_4x1_map.v
index 868f5d00..762e2938 100644
--- a/tests/techmap/mem_simple_4x1_map.v
+++ b/tests/techmap/mem_simple_4x1_map.v
@@ -1,5 +1,5 @@
-module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
+module \$mem (RD_CLK, RD_EN, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter MEMID = "";
parameter SIZE = 256;
parameter OFFSET = 0;
@@ -17,6 +17,7 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter WR_CLK_POLARITY = 1'b1;
input [RD_PORTS-1:0] RD_CLK;
+ input [RD_PORTS-1:0] RD_EN;
input [RD_PORTS*ABITS-1:0] RD_ADDR;
output reg [RD_PORTS*WIDTH-1:0] RD_DATA;
@@ -30,6 +31,8 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter _TECHMAP_CONNMAP_RD_CLK_ = 0;
parameter _TECHMAP_CONNMAP_WR_CLK_ = 0;
+ parameter _TECHMAP_CONSTVAL_RD_EN_ = 0;
+
parameter _TECHMAP_BITS_CONNMAP_ = 0;
parameter _TECHMAP_CONNMAP_WR_EN_ = 0;
@@ -46,6 +49,10 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
if (RD_PORTS > 1 || WR_PORTS > 1)
_TECHMAP_FAIL_ <= 1;
+ // read enable must be constant high
+ if (_TECHMAP_CONSTVAL_RD_EN_[0] !== 1'b1)
+ _TECHMAP_FAIL_ <= 1;
+
// we expect positive read clock and non-transparent reads
if (RD_TRANSPARENT || !RD_CLK_ENABLE || !RD_CLK_POLARITY)
_TECHMAP_FAIL_ <= 1;