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authorClifford Wolf <clifford@clifford.at>2013-11-18 19:55:39 +0100
committerClifford Wolf <clifford@clifford.at>2013-11-18 19:55:39 +0100
commitc5e26f839c93af7bab93bffdab518f2a877291d9 (patch)
treef1f6467889904f8de21901142381b6eccd75457e /tests
parent4f2edcf2f930f18a683a862b987fc36eb23f94c5 (diff)
Added additional mem2reg testcase
Diffstat (limited to 'tests')
-rw-r--r--tests/simple/mem2reg.v28
1 files changed, 28 insertions, 0 deletions
diff --git a/tests/simple/mem2reg.v b/tests/simple/mem2reg.v
index 7be32b0b..e2c136dd 100644
--- a/tests/simple/mem2reg.v
+++ b/tests/simple/mem2reg.v
@@ -1,3 +1,4 @@
+
module test1(in_addr, in_data, out_addr, out_data);
input [1:0] in_addr, out_addr;
@@ -15,3 +16,30 @@ always @* begin
end
endmodule
+
+// ------------------------------------------------------
+
+module test2(clk, mode, addr, data);
+
+input clk, mode;
+input [2:0] addr;
+output [3:0] data;
+
+(* mem2reg *)
+reg [3:0] mem [0:7];
+
+assign data = mem[addr];
+
+integer i;
+
+always @(posedge clk) begin
+ if (mode) begin
+ for (i=0; i<8; i=i+1)
+ mem[i] <= mem[i]+1;
+ end else begin
+ mem[addr] <= 0;
+ end
+end
+
+endmodule
+