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authorClifford Wolf <clifford@clifford.at>2015-05-11 21:46:35 +0200
committerClifford Wolf <clifford@clifford.at>2015-05-11 21:58:21 +0200
commitdae00e1d8301aae25f3432ca12995c9a3b380679 (patch)
treeb55a32f53afa4611a6c3a1ef824b2b22b95dcc2e /tests
parent42348cddd9218f198e93bc11909e7b118a71c9ba (diff)
changed file() to open() in python scripts
Diffstat (limited to 'tests')
-rw-r--r--tests/bram/generate.py8
-rw-r--r--tests/fsm/generate.py4
-rw-r--r--tests/realmath/generate.py6
-rw-r--r--tests/share/generate.py4
4 files changed, 11 insertions, 11 deletions
diff --git a/tests/bram/generate.py b/tests/bram/generate.py
index 2adfdcfb..766157eb 100644
--- a/tests/bram/generate.py
+++ b/tests/bram/generate.py
@@ -250,10 +250,10 @@ print("Rng seed: %d" % seed)
random.seed(seed)
for k1 in range(5):
- dsc_f = file("temp/brams_%02d.txt" % k1, "w")
- sim_f = file("temp/brams_%02d.v" % k1, "w")
- ref_f = file("temp/brams_%02d_ref.v" % k1, "w")
- tb_f = file("temp/brams_%02d_tb.v" % k1, "w")
+ dsc_f = open("temp/brams_%02d.txt" % k1, "w")
+ sim_f = open("temp/brams_%02d.v" % k1, "w")
+ ref_f = open("temp/brams_%02d_ref.v" % k1, "w")
+ tb_f = open("temp/brams_%02d_tb.v" % k1, "w")
for f in [sim_f, ref_f, tb_f]:
print("`timescale 1 ns / 1 ns", file=f)
diff --git a/tests/fsm/generate.py b/tests/fsm/generate.py
index fc67543f..352eedb0 100644
--- a/tests/fsm/generate.py
+++ b/tests/fsm/generate.py
@@ -34,7 +34,7 @@ def random_expr(variables):
raise AssertionError
for idx in range(50):
- with file('temp/uut_%05d.v' % idx, 'w') as f:
+ with open('temp/uut_%05d.v' % idx, 'w') as f:
with redirect_stdout(f):
rst2 = random.choice([False, True])
if rst2:
@@ -90,7 +90,7 @@ for idx in range(50):
print(' end')
print(' end')
print('endmodule')
- with file('temp/uut_%05d.ys' % idx, 'w') as f:
+ with open('temp/uut_%05d.ys' % idx, 'w') as f:
with redirect_stdout(f):
if test_verific:
print('read_verilog temp/uut_%05d.v' % idx)
diff --git a/tests/realmath/generate.py b/tests/realmath/generate.py
index 24d13561..16f68f05 100644
--- a/tests/realmath/generate.py
+++ b/tests/realmath/generate.py
@@ -40,7 +40,7 @@ def random_expression(depth = 3, maxparam = 0):
raise
for idx in range(100):
- with file('temp/uut_%05d.v' % idx, 'w') as f:
+ with open('temp/uut_%05d.v' % idx, 'w') as f:
with redirect_stdout(f):
print('module uut_%05d(output [63:0] %s);\n' % (idx, ', '.join(['y%02d' % i for i in range(100)])))
for i in range(30):
@@ -56,12 +56,12 @@ for idx in range(100):
for i in range(100):
print('assign y%02d = 65536 * (%s);' % (i, random_expression(maxparam = 60)))
print('endmodule')
- with file('temp/uut_%05d.ys' % idx, 'w') as f:
+ with open('temp/uut_%05d.ys' % idx, 'w') as f:
with redirect_stdout(f):
print('read_verilog uut_%05d.v' % idx)
print('rename uut_%05d uut_%05d_syn' % (idx, idx))
print('write_verilog uut_%05d_syn.v' % idx)
- with file('temp/uut_%05d_tb.v' % idx, 'w') as f:
+ with open('temp/uut_%05d_tb.v' % idx, 'w') as f:
with redirect_stdout(f):
print('module uut_%05d_tb;\n' % idx)
print('wire [63:0] %s;' % (', '.join(['r%02d' % i for i in range(100)])))
diff --git a/tests/share/generate.py b/tests/share/generate.py
index bb96fec6..7f8a5951 100644
--- a/tests/share/generate.py
+++ b/tests/share/generate.py
@@ -25,7 +25,7 @@ def maybe_plus_x(expr):
return expr
for idx in range(100):
- with file('temp/uut_%05d.v' % idx, 'w') as f:
+ with open('temp/uut_%05d.v' % idx, 'w') as f:
with redirect_stdout(f):
if random.choice(['bin', 'uni']) == 'bin':
print('module uut_%05d(a, b, c, d, x, s, y);' % (idx))
@@ -60,7 +60,7 @@ for idx in range(100):
random.choice(['', '$signed', '$unsigned']), op, maybe_plus_x('b'),
random_plus_x() if random.randint(0, 4) == 0 else ''))
print('endmodule')
- with file('temp/uut_%05d.ys' % idx, 'w') as f:
+ with open('temp/uut_%05d.ys' % idx, 'w') as f:
with redirect_stdout(f):
print('read_verilog temp/uut_%05d.v' % idx)
print('proc;;')