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authorClifford Wolf <clifford@clifford.at>2015-02-14 12:55:03 +0100
committerClifford Wolf <clifford@clifford.at>2015-02-14 12:55:03 +0100
commitdcf2e242406d563254013ea7db4b29b55be96eff (patch)
treead242e2b5273a775752a2398171c178df89f9e2a /tests
parent913c304fe62cb962e32fa0eb024fa4fc3110639c (diff)
Added $meminit support to "memory" command
Diffstat (limited to 'tests')
-rw-r--r--tests/simple/memory.v23
-rw-r--r--tests/techmap/mem_simple_4x1_map.v5
2 files changed, 13 insertions, 15 deletions
diff --git a/tests/simple/memory.v b/tests/simple/memory.v
index f7c37309..23e93ac9 100644
--- a/tests/simple/memory.v
+++ b/tests/simple/memory.v
@@ -209,29 +209,22 @@ endmodule
module memtest09 (
input clk,
- input [1:0] a_addr, a_din, b_addr, b_din,
+ input [3:0] a_addr, a_din, b_addr, b_din,
input a_wen, b_wen,
- output reg [1:0] a_dout, b_dout
+ output reg [3:0] a_dout, b_dout
);
- reg [1:0] memory [0:3];
-
- initial begin
- memory[0] <= 0;
- memory[1] <= 1;
- memory[2] <= 2;
- memory[3] <= 3;
- end
+ reg [3:0] memory [0:35];
always @(posedge clk) begin
if (a_wen)
- memory[a_addr] <= a_din;
- a_dout <= memory[a_addr];
+ memory[10 + a_addr] <= a_din;
+ a_dout <= memory[10 + a_addr];
end
always @(posedge clk) begin
- if (b_wen)
- memory[b_addr] <= b_din;
- b_dout <= memory[b_addr];
+ if (b_wen && (10 + a_addr != 20 + b_addr))
+ memory[20 + b_addr] <= b_din;
+ b_dout <= memory[20 + b_addr];
end
endmodule
diff --git a/tests/techmap/mem_simple_4x1_map.v b/tests/techmap/mem_simple_4x1_map.v
index 820f89de..868f5d00 100644
--- a/tests/techmap/mem_simple_4x1_map.v
+++ b/tests/techmap/mem_simple_4x1_map.v
@@ -5,6 +5,7 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
parameter OFFSET = 0;
parameter ABITS = 8;
parameter WIDTH = 8;
+ parameter signed INIT = 1'bx;
parameter RD_PORTS = 1;
parameter RD_CLK_ENABLE = 1'b1;
@@ -37,6 +38,10 @@ module \$mem (RD_CLK, RD_ADDR, RD_DATA, WR_CLK, WR_EN, WR_ADDR, WR_DATA);
initial begin
_TECHMAP_FAIL_ <= 0;
+ // no initialized memories
+ if (INIT !== 1'bx)
+ _TECHMAP_FAIL_ <= 1;
+
// only map cells with only one read and one write port
if (RD_PORTS > 1 || WR_PORTS > 1)
_TECHMAP_FAIL_ <= 1;