diff options
| -rw-r--r-- | passes/cmds/select.cc | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc index 99f9d31e..ed3e4d72 100644 --- a/passes/cmds/select.cc +++ b/passes/cmds/select.cc @@ -657,6 +657,21 @@ static void select_stmt(RTLIL::Design *design, std::string arg) if (match_ids(it.first, arg_memb.substr(2))) sel.selected_members[mod->name].insert(it.first); } else + if (arg_memb.substr(0, 2) == "i:") { + for (auto &it : mod->wires) + if (it.second->port_input && match_ids(it.first, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(it.first); + } else + if (arg_memb.substr(0, 2) == "o:") { + for (auto &it : mod->wires) + if (it.second->port_output && match_ids(it.first, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(it.first); + } else + if (arg_memb.substr(0, 2) == "x:") { + for (auto &it : mod->wires) + if ((it.second->port_input || it.second->port_output) && match_ids(it.first, arg_memb.substr(2))) + sel.selected_members[mod->name].insert(it.first); + } else if (arg_memb.substr(0, 2) == "m:") { for (auto &it : mod->memories) if (match_ids(it.first, arg_memb.substr(2))) @@ -836,6 +851,9 @@ struct SelectPass : public Pass { log(" w:<pattern>\n"); log(" all wires with a name matching the given wildcard pattern\n"); log("\n"); + log(" i:<pattern>, o:<pattern>, x:<pattern>\n"); + log(" select input (i:), output (o:) or any ports (x:) with matching names\n"); + log("\n"); log(" m:<pattern>\n"); log(" all memories with a name matching the given pattern\n"); log("\n"); |