diff options
| -rw-r--r-- | kernel/rtlil.cc | 15 | ||||
| -rw-r--r-- | kernel/rtlil.h | 1 | ||||
| -rw-r--r-- | passes/fsm/fsm_extract.cc | 4 | ||||
| -rw-r--r-- | passes/opt/opt_const.cc | 19 |
4 files changed, 38 insertions, 1 deletions
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 8c0b41d0..bf0fd1c8 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -3000,6 +3000,21 @@ bool RTLIL::SigSpec::is_fully_const() const return true; } +bool RTLIL::SigSpec::is_fully_zero() const +{ + cover("kernel.rtlil.sigspec.is_fully_zero"); + + pack(); + for (auto it = chunks_.begin(); it != chunks_.end(); it++) { + if (it->width > 0 && it->wire != NULL) + return false; + for (size_t i = 0; i < it->data.size(); i++) + if (it->data[i] != RTLIL::State::S0) + return false; + } + return true; +} + bool RTLIL::SigSpec::is_fully_def() const { cover("kernel.rtlil.sigspec.is_fully_def"); diff --git a/kernel/rtlil.h b/kernel/rtlil.h index 956b303f..e9deb1d5 100644 --- a/kernel/rtlil.h +++ b/kernel/rtlil.h @@ -692,6 +692,7 @@ public: bool is_chunk() const; bool is_fully_const() const; + bool is_fully_zero() const; bool is_fully_def() const; bool is_fully_undef() const; bool has_const() const; diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc index 68667ef0..b5250970 100644 --- a/passes/fsm/fsm_extract.cc +++ b/passes/fsm/fsm_extract.cc @@ -305,7 +305,9 @@ static void extract_fsm(RTLIL::Wire *wire) for (auto &cellport : cellport_list) { RTLIL::Cell *cell = module->cells_.at(cellport.first); RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); - RTLIL::SigSpec sig_b = assign_map(cell->getPort("\\B")); + RTLIL::SigSpec sig_b; + if (cell->hasPort("\\B")) + sig_b = assign_map(cell->getPort("\\B")); RTLIL::SigSpec sig_y = assign_map(cell->getPort("\\Y")); if (cellport.second == "\\A" && !sig_b.is_fully_const()) continue; diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc index 1758a34f..859d7c64 100644 --- a/passes/opt/opt_const.cc +++ b/passes/opt/opt_const.cc @@ -548,6 +548,25 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons } } + if ((cell->type == "$eq" || cell->type == "$ne") && + (assign_map(cell->getPort("\\A")).is_fully_zero() || assign_map(cell->getPort("\\B")).is_fully_zero())) + { + cover_list("opt.opt_const.eqneq.cmpzero", "$eq", "$ne", cell->type.str()); + log("Replacing %s cell `%s' in module `%s' with %s.\n", log_id(cell->type), log_id(cell), + log_id(module), "$eq" ? "$logic_not" : "$reduce_bool"); + cell->type = cell->type == "$eq" ? "$logic_not" : "$reduce_bool"; + if (assign_map(cell->getPort("\\A")).is_fully_zero()) { + cell->setPort("\\A", cell->getPort("\\B")); + cell->setParam("\\A_SIGNED", cell->getParam("\\B_SIGNED")); + cell->setParam("\\A_WIDTH", cell->getParam("\\B_WIDTH")); + } + cell->unsetPort("\\B"); + cell->unsetParam("\\B_SIGNED"); + cell->unsetParam("\\B_WIDTH"); + did_something = true; + goto next_cell; + } + if (cell->type.in("$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx") && assign_map(cell->getPort("\\B")).is_fully_const()) { bool sign_ext = cell->type == "$sshr" && cell->getParam("\\A_SIGNED").as_bool(); |