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-rw-r--r--README33
-rw-r--r--passes/abc/abc.cc28
-rw-r--r--tests/openmsp430/.gitignore3
-rwxr-xr-x[-rw-r--r--]tests/openmsp430/run-synth.sh0
-rwxr-xr-xtests/simple/run-test.sh7
5 files changed, 49 insertions, 22 deletions
diff --git a/README b/README
index 7512f767..89aa0544 100644
--- a/README
+++ b/README
@@ -29,36 +29,37 @@ synthesis algorithms for various application domains.
Yosys can be adapted to perform any synthesis job by combining
the existing passes (algorithms) using synthesis scripts and
-adding additional passes as needed by extending the yosys c++
-codebase.
+adding additional passes as needed by extending the yosys C++
+code base.
Yosys is free software licensed under the ISC license (a GPL
-compatible licence that is similar in terms to the MIT license
+compatible license that is similar in terms to the MIT license
or the 2-clause BSD license).
Getting Started
===============
-To build Yosys simply typoe 'make' in this directory. You need
+To build Yosys simply type 'make' in this directory. You need
a C++ compiler with C++11 support (up-to-date CLANG or GCC is
recommended) and some standard tools such as GNU Flex, GNU Bison,
-and GNU Make. It might be neccessary to make some changes to
-the config section of the Makefile.
+and GNU Make. It might be necessary to make some changes to
+the config section of the Makefile. The extensive tests require
+Icarus Verilog.
$ vi Makefile
$ make
$ make test
$ sudo make install
-Yosys can be used using the interactive command shell, using
-synthesis scripts or using command line arguments. Let's perform
+Yosys can be used with the interactive command shell, with
+synthesis scripts or with command line arguments. Let's perform
a simple synthesis job using the interactive command shell:
$ ./yosys
yosys>
-the command "help" can be used to pritn a list of all available
+the command "help" can be used to print a list of all available
commands and "help <command>" to print details on the specified command:
yosys> help help
@@ -71,7 +72,7 @@ writing the design to the console in yosys's internal format:
yosys> write_ilang
-convert processes (always blocks) to netlist elements and perform
+convert processes ("always" blocks) to netlist elements and perform
some simple optimizations:
yosys> proc; opt
@@ -178,7 +179,7 @@ Verilog Attributes and non-standard features
is strongly recommended instead).
- The "nomem2reg" attribute on modules or arrays prohibits the
- automatic early conversion of arrays to seperate registers.
+ automatic early conversion of arrays to separate registers.
- The "nolatches" attribute on modules or always-blocks
prohibits the generation of logic-loops for latches. Instead
@@ -188,7 +189,7 @@ Verilog Attributes and non-standard features
the non-standard {* ... *} attribute syntax to set default attributes
for everything that comes after the {* ... *} statement. (Reset
by adding an empty {* *} statement.) The preprocessor define
- __YOSYS_ENABLE_DEFATTR__ must be set in order for this featre to be active.
+ __YOSYS_ENABLE_DEFATTR__ must be set in order for this feature to be active.
TODOs / Open Bugs
@@ -196,7 +197,7 @@ TODOs / Open Bugs
- Write "design and implementation of.." document
-- Add brief sourcecode documentation to:
+- Add brief source code documentation to:
- Most passes and kernel functionalities
@@ -206,10 +207,10 @@ TODOs / Open Bugs
- Constant functions
- Indexed part selects
- Multi-dimensional arrays
- - ROM modelling using "initial" blocks
+ - ROM modeling using "initial" blocks
- The "defparam <cell_name>.<parameter_name> = <value>;" syntax
- - Builtin primitive gates (and, nand, cmos, nmos, pmos, etc..)
- - Ignore what needs to be ignored (e.g. drive and charge strenghts)
+ - Built-in primitive gates (and, nand, cmos, nmos, pmos, etc..)
+ - Ignore what needs to be ignored (e.g. drive and charge strengths)
- Check standard vs. implementation to identify missing features
- Actually use range information on parameters
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index acd93546..e8f0a144 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -332,7 +332,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
tempdir_name[0] = tempdir_name[4] = '_';
char *p = mkdtemp(tempdir_name);
log_header("Extracting gate logic of module `%s' to `%s/input.v'..\n", module->name.c_str(), tempdir_name);
- assert(p != NULL);
+ if (p == NULL)
+ log_error("For some reason mkdtemp() failed!\n");
std::vector<RTLIL::Cell*> cells;
cells.reserve(module->cells.size());
@@ -355,7 +356,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
if (asprintf(&p, "%s/input.v", tempdir_name) < 0) abort();
FILE *f = fopen(p, "wt");
- assert(f != NULL);
+ if (f == NULL);
+ log_error("Opening %s for writing failed: %s\n", p, strerrno(errno));
free(p);
fprintf(f, "module logic (");
@@ -418,7 +420,8 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
if (asprintf(&p, "%s/stdcells.genlib", tempdir_name) < 0) abort();
f = fopen(p, "wt");
- assert(f != NULL);
+ if (f == NULL);
+ log_error("Opening %s for writing failed: %s\n", p, strerrno(errno));
fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
fprintf(f, "GATE ONE 1 Y=CONST1;\n");
fprintf(f, "GATE BUF 1 Y=A; PIN * NONINV 1 999 1 0 1 0\n");
@@ -441,10 +444,23 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
else
snprintf(buffer, 1024, "%s -c 'read_verilog %s/input.v; read_library %s/stdcells.genlib; "
"map; write_verilog %s/output.v' 2>&1", exe_file.c_str(), tempdir_name, tempdir_name, tempdir_name);
+ errno = ENOMEM; // popen does not set errno if memory allocation fails, therefore set it by hand
f = popen(buffer, "r");
+ if (f == NULL)
+ log_error("Opening pipe to `%s' for reading failed: %s\n", buffer, strerrno(errno));
while (fgets(buffer, 1024, f) != NULL)
log("ABC: %s", buffer);
- fclose(f);
+ errno = 0;
+ int ret = pclose(f);
+ if (ret < 0)
+ log_error("Closing pipe to `%s' failed: %s\n", buffer, strerrno(errno));
+ if (WEXITSTATUS(ret) != 0) {
+ switch (WEXITSTATUS(ret)) {
+ case 127: log_error("ABC: execution of command \"%s\" failed: Command not found\n", exe_file.c_str()); break;
+ case 126: log_error("ABC: execution of command \"%s\" failed: Command not executable\n", exe_file.c_str()); break;
+ default: log_error("ABC: execution of command \"%s\" failed: the shell returned %d\n", exe_file.c_str(), WEXITSTATUS(ret)); break;
+ }
+ }
if (asprintf(&p, "%s/output.v", tempdir_name) < 0) abort();
f = fopen(p, "rt");
@@ -627,10 +643,10 @@ struct AbcPass : public Pass {
log(" keeps using yosys's internal gate library.\n");
log("\n");
log(" -nocleanup\n");
- log(" when this option is used, the tempprary files created be this pass\n");
+ log(" when this option is used, the temporary files created by this pass\n");
log(" are not removed. this is useful for debugging.\n");
log("\n");
- log("This pass does not operate on modules with uprocessed processes in it.\n");
+ log("This pass does not operate on modules with unprocessed processes in it.\n");
log("(I.e. the 'proc' pass should be used first to convert processes to netlists.)\n");
log("\n");
log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
diff --git a/tests/openmsp430/.gitignore b/tests/openmsp430/.gitignore
new file mode 100644
index 00000000..eaf13a59
--- /dev/null
+++ b/tests/openmsp430/.gitignore
@@ -0,0 +1,3 @@
+fsm_info.txt
+synth.v
+synth.log
diff --git a/tests/openmsp430/run-synth.sh b/tests/openmsp430/run-synth.sh
index e4d6bc72..e4d6bc72 100644..100755
--- a/tests/openmsp430/run-synth.sh
+++ b/tests/openmsp430/run-synth.sh
diff --git a/tests/simple/run-test.sh b/tests/simple/run-test.sh
index bf27d15f..eb6fd10b 100755
--- a/tests/simple/run-test.sh
+++ b/tests/simple/run-test.sh
@@ -1,3 +1,10 @@
#!/bin/bash
+
+# check for Icarus Verilog
+if ! which iverilog > /dev/null ; then
+ echo "$0: Error: Icarus Verilog 'iverilog' not found."
+ exit 1
+fi
+
make -C ../.. || exit 1
exec bash ../tools/autotest.sh *.v