diff options
| -rw-r--r-- | passes/cmds/Makefile.inc | 1 | ||||
| -rw-r--r-- | passes/cmds/setundef.cc | 157 |
2 files changed, 158 insertions, 0 deletions
diff --git a/passes/cmds/Makefile.inc b/passes/cmds/Makefile.inc index 9e96ff36..ea70f40c 100644 --- a/passes/cmds/Makefile.inc +++ b/passes/cmds/Makefile.inc @@ -6,6 +6,7 @@ OBJS += passes/cmds/show.o OBJS += passes/cmds/rename.o OBJS += passes/cmds/connect.o OBJS += passes/cmds/scatter.o +OBJS += passes/cmds/setundef.o OBJS += passes/cmds/splitnets.o OBJS += passes/cmds/stat.o diff --git a/passes/cmds/setundef.cc b/passes/cmds/setundef.cc new file mode 100644 index 00000000..394834a3 --- /dev/null +++ b/passes/cmds/setundef.cc @@ -0,0 +1,157 @@ +/* + * yosys -- Yosys Open SYnthesis Suite + * + * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +#include "kernel/register.h" +#include "kernel/celltypes.h" +#include "kernel/sigtools.h" +#include "kernel/rtlil.h" +#include "kernel/log.h" + +static int next_bit_mode; +static uint32_t next_bit_state; + +static RTLIL::State next_bit() +{ + if (next_bit_mode == 0) + return RTLIL::State::S0; + + if (next_bit_mode == 1) + return RTLIL::State::S1; + + // xorshift32 + next_bit_state ^= next_bit_state << 13; + next_bit_state ^= next_bit_state >> 17; + next_bit_state ^= next_bit_state << 5; + log_assert(next_bit_state != 0); + + return ((next_bit_state >> (next_bit_state & 15)) & 1) ? RTLIL::State::S0 : RTLIL::State::S1; +} + +struct SetundefWorker +{ + void operator()(RTLIL::SigSpec &sig) + { + sig.expand(); + for (auto &c : sig.chunks) + if (c.wire == NULL && c.data.bits.at(0) > RTLIL::State::S1) + c.data.bits.at(0) = next_bit(); + sig.optimize(); + } +}; + +struct SetundefPass : public Pass { + SetundefPass() : Pass("setundef", "replace undef values with defined constants") { } + virtual void help() + { + // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| + log("\n"); + log(" setundef [options] [selection]\n"); + log("\n"); + log("This command replaced undef (x) constants with defined (0/1) constants.\n"); + log("\n"); + log(" -undriven\n"); + log(" also set undriven nets to constant values\n"); + log("\n"); + log(" -zero\n"); + log(" replace with bits cleared (0)\n"); + log("\n"); + log(" -one\n"); + log(" replace with bits set (1)\n"); + log("\n"); + log(" -random <seed>\n"); + log(" replace with random bits using the specified integer als seed\n"); + log(" value for the random number generator.\n"); + log("\n"); + } + virtual void execute(std::vector<std::string> args, RTLIL::Design *design) + { + bool got_value = false; + bool undriven_mode = false; + + size_t argidx; + for (argidx = 1; argidx < args.size(); argidx++) + { + if (args[argidx] == "-undriven") { + undriven_mode = true; + continue; + } + if (args[argidx] == "-zero") { + got_value = true; + next_bit_mode = 0; + continue; + } + if (args[argidx] == "-one") { + got_value = true; + next_bit_mode = 1; + continue; + } + if (args[argidx] == "-random" && !got_value && argidx+1 < args.size()) { + got_value = true; + next_bit_mode = 2; + next_bit_state = atoi(args[++argidx].c_str()) + 1; + for (int i = 0; i < 10; i++) + next_bit(); + continue; + } + break; + } + extra_args(args, argidx, design); + + if (!got_value) + log_cmd_error("One of the options -zero, -one, or -random <seed> must be specified.\n"); + + for (auto &mod_it : design->modules) + { + RTLIL::Module *module = mod_it.second; + if (!design->selected(module)) + continue; + + if (undriven_mode) + { + if (!module->processes.empty()) + log_error("The 'setundef' command can't operate in -undriven mode on modules with processes. Run 'proc' first.\n"); + + SigMap sigmap(module); + SigPool undriven_signals; + + for (auto &it : module->wires) + if (!it.second->port_input) + undriven_signals.add(sigmap(it.second)); + + CellTypes ct(design); + for (auto &it : module->cells) + for (auto &conn : it.second->connections) + if (!ct.cell_known(it.second->type) || ct.cell_output(it.second->type, conn.first)) + undriven_signals.del(sigmap(conn.second)); + + RTLIL::SigSpec sig = undriven_signals.export_all(); + for (auto &c : sig.chunks) { + RTLIL::SigSpec bits; + for (int i = 0; i < c.width; i++) + bits.append(next_bit()); + bits.optimize(); + module->connections.push_back(RTLIL::SigSig(c, bits)); + } + } + + module->rewrite_sigspecs(SetundefWorker()); + } + } +} SetundefPass; + |