diff options
| -rw-r--r-- | techlibs/common/Makefile.inc | 14 | ||||
| -rw-r--r-- | techlibs/common/blackbox.sed | 4 | ||||
| -rw-r--r-- | techlibs/common/simcells.v (renamed from techlibs/common/stdcells_sim.v) | 9 | ||||
| -rw-r--r-- | techlibs/common/simlib.v | 16 | ||||
| -rwxr-xr-x | tests/i2c_bench/run-test.sh | 2 | ||||
| -rwxr-xr-x | tests/tools/autotest.sh | 2 |
6 files changed, 25 insertions, 22 deletions
diff --git a/techlibs/common/Makefile.inc b/techlibs/common/Makefile.inc index e81d34fb..e2e1ba25 100644 --- a/techlibs/common/Makefile.inc +++ b/techlibs/common/Makefile.inc @@ -1,13 +1,21 @@ EXTRA_TARGETS += techlibs/common/blackbox.v -techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.v techlibs/common/stdcells_sim.v - cat techlibs/common/simlib.v techlibs/common/stdcells_sim.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new +techlibs/common/blackbox.v: techlibs/common/blackbox.sed techlibs/common/simlib.v techlibs/common/simcells.v + cat techlibs/common/simlib.v techlibs/common/simcells.v | sed -rf techlibs/common/blackbox.sed > techlibs/common/blackbox.v.new mv techlibs/common/blackbox.v.new techlibs/common/blackbox.v -EXTRA_TARGETS += share/simlib.v +EXTRA_TARGETS += share/simlib.v share/simcells.v share/blackbox.v share/simlib.v: techlibs/common/simlib.v mkdir -p share cp techlibs/common/simlib.v share/simlib.v +share/simcells.v: techlibs/common/simcells.v + mkdir -p share + cp techlibs/common/simcells.v share/simcells.v + +share/blackbox.v: techlibs/common/blackbox.v + mkdir -p share + cp techlibs/common/blackbox.v share/blackbox.v + diff --git a/techlibs/common/blackbox.sed b/techlibs/common/blackbox.sed index 4e9a3a7c..21693ecd 100644 --- a/techlibs/common/blackbox.sed +++ b/techlibs/common/blackbox.sed @@ -1,4 +1,4 @@ #!/bin/sed -r -/^(wire|assign|reg)/ d; -/^(genvar|always|initial)/,/^end/ d; +/^(wire|assign|reg|event)/ d; +/^(genvar|generate|always|initial)/,/^end/ d; s/ reg / /; diff --git a/techlibs/common/stdcells_sim.v b/techlibs/common/simcells.v index 88284a09..10a809db 100644 --- a/techlibs/common/stdcells_sim.v +++ b/techlibs/common/simcells.v @@ -51,13 +51,8 @@ endmodule module \$_MUX_ (A, B, S, Y); input A, B, S; -output reg Y; -always @* begin - if (S) - Y = B; - else - Y = A; -end +output Y; +assign Y = S ? B : A; endmodule module \$_SR_NN_ (S, R, Q); diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v index beb2b885..b4440ea8 100644 --- a/techlibs/common/simlib.v +++ b/techlibs/common/simlib.v @@ -31,13 +31,11 @@ * */ -`define INPUT_A \ -input [A_WIDTH-1:0] A; \ -generate if (A_SIGNED) begin:A_BUF wire signed [A_WIDTH-1:0] val = A; end else begin:A_BUF wire [A_WIDTH-1:0] val = A; end endgenerate +`define INPUT_A input [A_WIDTH-1:0] A; \ + generate if (A_SIGNED) begin:A_BUF wire signed [A_WIDTH-1:0] val = A; end else begin:A_BUF wire [A_WIDTH-1:0] val = A; end endgenerate -`define INPUT_B \ -input [B_WIDTH-1:0] B; \ -generate if (B_SIGNED) begin:B_BUF wire signed [B_WIDTH-1:0] val = B; end else begin:B_BUF wire [B_WIDTH-1:0] val = B; end endgenerate +`define INPUT_B input [B_WIDTH-1:0] B; \ + generate if (B_SIGNED) begin:B_BUF wire signed [B_WIDTH-1:0] val = B; end else begin:B_BUF wire [B_WIDTH-1:0] val = B; end endgenerate // -------------------------------------------------------- @@ -661,7 +659,7 @@ generate end endgenerate -always @* +always @* begin casez ({I[WIDTH-1], lut0_out, lut1_out}) 3'b?11: O = 1'b1; 3'b?00: O = 1'b0; @@ -669,6 +667,7 @@ always @* 3'b1??: O = lut1_out; default: O = 1'bx; endcase +end endmodule @@ -784,9 +783,10 @@ input EN; input [WIDTH-1:0] D; output reg [WIDTH-1:0] Q; -always @* +always @* begin if (EN == EN_POLARITY) Q <= D; +end endmodule diff --git a/tests/i2c_bench/run-test.sh b/tests/i2c_bench/run-test.sh index 580ce4c0..865f9ad3 100755 --- a/tests/i2c_bench/run-test.sh +++ b/tests/i2c_bench/run-test.sh @@ -28,7 +28,7 @@ EOT vlogcomp --work syn i2c_master_syn.v vlogcomp --work syn ../../techlibs/common/simlib.v -vlogcomp --work syn ../../techlibs/common/stdcells_sim.v +vlogcomp --work syn ../../techlibs/common/simcells.v vlogcomp --work syn i2c_slave_model.v vlogcomp --work syn spi_slave_model.v vlogcomp --work syn tst_bench_top.v diff --git a/tests/tools/autotest.sh b/tests/tools/autotest.sh index 3d7601eb..5a302bcd 100755 --- a/tests/tools/autotest.sh +++ b/tests/tools/autotest.sh @@ -139,7 +139,7 @@ do compile_and_run ${bn}_tb_syn${test_count} ${bn}_out_syn${test_count} \ ${bn}_tb.v ${bn}_syn${test_count}.v $libs \ "$toolsdir"/../../techlibs/common/simlib.v \ - "$toolsdir"/../../techlibs/common/stdcells_sim.v + "$toolsdir"/../../techlibs/common/simcells.v if $genvcd; then mv testbench.vcd ${bn}_syn${test_count}.vcd; fi $toolsdir/cmp_tbdata ${bn}_out_ref ${bn}_out_syn${test_count} test_count=$(( test_count + 1 )) |