diff options
| -rw-r--r-- | README | 6 | ||||
| -rw-r--r-- | passes/opt/opt_clean.cc | 5 |
2 files changed, 8 insertions, 3 deletions
@@ -254,9 +254,9 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The verilog backend also does not output placeholder modules on default. -- The "keep" attribute on cells is used to mark cells that should never be - removed by the optimizer. This is used for example for cells that have - hidden connections that are not part of the netlist, such as IO pads. +- The "keep" attribute on cells and wires is used to mark objects that should + never be removed by the optimizer. This is used for example for cells that + have hidden connections that are not part of the netlist, such as IO pads. - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 3d75b640..8e3691b3 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -190,6 +190,11 @@ static void rmunused_module_signals(RTLIL::Module *module, bool purge_mode, bool if (!wire->port_input) used_signals_nodrivers.add(sig); } + if (wire->get_bool_attribute("\\keep")) { + RTLIL::SigSpec sig = RTLIL::SigSpec(wire); + assign_map.apply(sig); + used_signals.add(sig); + } } std::vector<RTLIL::Wire*> del_wires; |