diff options
| -rw-r--r-- | passes/techmap/techmap.cc | 9 | ||||
| -rw-r--r-- | techlibs/xilinx/synth_xilinx.cc | 8 |
2 files changed, 13 insertions, 4 deletions
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c3af697b..551fc578 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -372,6 +372,11 @@ struct TechmapPass : public Pass { log(" transforms the internal RTL cells to the internal gate\n"); log(" library.\n"); log("\n"); + log(" -share_map filename\n"); + log(" like -map, but look for the file in the share directory (where the\n"); + log(" yosys data files are). this is mainly used internally when techmap\n"); + log(" is called from other commands.\n"); + log("\n"); log("When a module in the map file has the 'techmap_celltype' attribute set, it will\n"); log("match cells with a type that match the text value of this attribute.\n"); log("\n"); @@ -423,6 +428,10 @@ struct TechmapPass : public Pass { map_files.push_back(args[++argidx]); continue; } + if (args[argidx] == "-share_map" && argidx+1 < args.size()) { + map_files.push_back(get_share_file_name(args[++argidx])); + continue; + } break; } extra_args(args, argidx, design); diff --git a/techlibs/xilinx/synth_xilinx.cc b/techlibs/xilinx/synth_xilinx.cc index 78c7a8af..ff906db8 100644 --- a/techlibs/xilinx/synth_xilinx.cc +++ b/techlibs/xilinx/synth_xilinx.cc @@ -82,7 +82,7 @@ struct SynthXilinxPass : public Pass { log(" clean\n"); log("\n"); log(" map_cells:\n"); - log(" techmap -map <share_dir>/xilinx/cells.v\n"); + log(" techmap -share_map xilinx/cells.v\n"); log(" clean\n"); log("\n"); log(" clkbuf:\n"); @@ -94,7 +94,7 @@ struct SynthXilinxPass : public Pass { log(" iopadmap -outpad OBUF I:O -inpad IBUF O:I @xilinx_nonclocks\n"); log("\n"); log(" edif:\n"); - log(" write_edif -top <top> synth.edif\n"); + log(" write_edif synth.edif\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) @@ -182,7 +182,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "map_cells")) { - Pass::call(design, stringf("techmap -map %s", get_share_file_name("xilinx/cells.v").c_str())); + Pass::call(design, "techmap -share_map xilinx/cells.v"); Pass::call(design, "clean"); } @@ -201,7 +201,7 @@ struct SynthXilinxPass : public Pass { if (check_label(active, run_from, run_to, "edif")) { if (!edif_file.empty()) - Pass::call(design, stringf("write_edif -top %s %s", top_module.c_str(), edif_file.c_str())); + Pass::call(design, stringf("write_edif %s", edif_file.c_str())); } log_pop(); |