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-rw-r--r--frontends/ast/simplify.cc2
-rw-r--r--passes/fsm/fsmdata.h8
2 files changed, 5 insertions, 5 deletions
diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index f819b250..d86bfb3f 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -2259,7 +2259,7 @@ AstNode *AstNode::eval_const_function(AstNode *fcall)
log_error("Non-constant range in %s:%d (called from %s:%d).\n",
range->filename.c_str(), range->linenum, fcall->filename.c_str(), fcall->linenum);
int offset = std::min(range->range_left, range->range_right);
- int width = std::min(std::abs(range->range_left - range->range_right) + 1, width);
+ int width = std::abs(range->range_left - range->range_right) + 1;
varinfo_t &v = variables[stmt->children.at(0)->str];
RTLIL::Const r = stmt->children.at(1)->bitsAsConst(v.val.bits.size());
for (int i = 0; i < width; i++)
diff --git a/passes/fsm/fsmdata.h b/passes/fsm/fsmdata.h
index d0be71c5..ae9569ed 100644
--- a/passes/fsm/fsmdata.h
+++ b/passes/fsm/fsmdata.h
@@ -143,25 +143,25 @@ struct FsmData
log(" Input signals:\n");
RTLIL::SigSpec sig_in = cell->connections["\\CTRL_IN"];
for (int i = 0; i < SIZE(sig_in); i++)
- log(" %3zd: %s\n", i, log_signal(sig_in[i]));
+ log(" %3d: %s\n", i, log_signal(sig_in[i]));
log("\n");
log(" Output signals:\n");
RTLIL::SigSpec sig_out = cell->connections["\\CTRL_OUT"];
for (int i = 0; i < SIZE(sig_out); i++)
- log(" %3zd: %s\n", i, log_signal(sig_out[i]));
+ log(" %3d: %s\n", i, log_signal(sig_out[i]));
log("\n");
log(" State encoding:\n");
for (int i = 0; i < SIZE(state_table); i++)
- log(" %3zd: %10s%s\n", i, log_signal(state_table[i], false),
+ log(" %3d: %10s%s\n", i, log_signal(state_table[i], false),
int(i) == reset_state ? " <RESET STATE>" : "");
log("\n");
log(" Transition Table (state_in, ctrl_in, state_out, ctrl_out):\n");
for (int i = 0; i < SIZE(transition_table); i++) {
transition_t &tr = transition_table[i];
- log(" %5zd: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));
+ log(" %5d: %5d %s -> %5d %s\n", i, tr.state_in, log_signal(tr.ctrl_in), tr.state_out, log_signal(tr.ctrl_out));
}
log("\n");