diff options
| -rw-r--r-- | btor.ys | 11 | ||||
| -rwxr-xr-x | verilog2btor.sh | 26 |
2 files changed, 28 insertions, 9 deletions
@@ -1,10 +1,3 @@ -#design should be loaded before executing -#set the: hierarchy -top <module_top> -#set the: hierarchy -libdir <dir> - -#high level synthesis -################# -#converting processes to cells proc; opt; opt_const -mux_undef; opt; rename -hide;;; @@ -17,6 +10,6 @@ flatten;; memory_unpack; #cell output to be a single wire splitnets -driver; +setundef -zero -undriven; opt;;; -#writing btor -write_btor design.btor; + diff --git a/verilog2btor.sh b/verilog2btor.sh new file mode 100755 index 00000000..e01d1508 --- /dev/null +++ b/verilog2btor.sh @@ -0,0 +1,26 @@ +#!/bin/sh + +# +# Script to writing btor from verilog design +# + +if [ "$#" -ne 3 ]; then + echo "Usage: $0 input.v output.btor top-module-name" >&2 + exit 1 +fi +if ! [ -e "$1" ]; then + echo "$1 not found" >&2 + exit 1 +fi + +FULL_PATH=$(readlink -f $1) +DIR=$(dirname $FULL_PATH) + +./yosys -p " +read_verilog $1; +hierarchy -top $3; +hierarchy -libdir $DIR; +hierarchy -check; +script btor.ys; +write_btor $2;" + |