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-rw-r--r--techlibs/common/simlib.v22
1 files changed, 12 insertions, 10 deletions
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index e522e37c..0e041e12 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -715,17 +715,19 @@ generate
\$lut #( .WIDTH(WIDTH-1), .LUT(LUT ) ) lut0 ( .I(I[WIDTH-2:0]), .O(lut0_out) );
\$lut #( .WIDTH(WIDTH-1), .LUT(LUT >> (2**(WIDTH-1))) ) lut1 ( .I(I[WIDTH-2:0]), .O(lut1_out) );
end
-endgenerate
-always @* begin
- casez ({I[WIDTH-1], lut0_out, lut1_out})
- 3'b?11: O = 1'b1;
- 3'b?00: O = 1'b0;
- 3'b0??: O = lut0_out;
- 3'b1??: O = lut1_out;
- default: O = 1'bx;
- endcase
-end
+ if (WIDTH > 0) begin:lutlogic
+ always @* begin
+ casez ({I[WIDTH-1], lut0_out, lut1_out})
+ 3'b?11: O = 1'b1;
+ 3'b?00: O = 1'b0;
+ 3'b0??: O = lut0_out;
+ 3'b1??: O = lut1_out;
+ default: O = 1'bx;
+ endcase
+ end
+ end
+endgenerate
endmodule