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-rw-r--r--frontends/ast/genrtlil.cc66
-rw-r--r--frontends/ilang/parser.y43
-rw-r--r--kernel/rtlil.h3
3 files changed, 18 insertions, 94 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 681b3486..34a3f1ba 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -56,15 +56,6 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
wire->width = result_width;
current_module->wires[wire->name] = wire;
- RTLIL::SigChunk chunk;
- chunk.wire = wire;
- chunk.width = wire->width;
- chunk.offset = 0;
-
- RTLIL::SigSpec sig;
- sig.chunks().push_back(chunk);
- sig.size() = chunk.width;
-
if (gen_attributes)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
@@ -78,8 +69,8 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
cell->connections["\\A"] = arg;
cell->parameters["\\Y_WIDTH"] = result_width;
- cell->connections["\\Y"] = sig;
- return sig;
+ cell->connections["\\Y"] = wire;
+ return wire;
}
// helper function for extending bit width (preferred over SigSpec::extend() because of correct undef propagation in ConstEval)
@@ -105,15 +96,6 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
wire->width = width;
current_module->wires[wire->name] = wire;
- RTLIL::SigChunk chunk;
- chunk.wire = wire;
- chunk.width = wire->width;
- chunk.offset = 0;
-
- RTLIL::SigSpec new_sig;
- new_sig.chunks().push_back(chunk);
- new_sig.size() = chunk.width;
-
if (that != NULL)
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
@@ -127,8 +109,8 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
cell->connections["\\A"] = sig;
cell->parameters["\\Y_WIDTH"] = width;
- cell->connections["\\Y"] = new_sig;
- sig = new_sig;
+ cell->connections["\\Y"] = wire;
+ sig = wire;
}
// helper function for creating RTLIL code for binary operations
@@ -149,15 +131,6 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
wire->width = result_width;
current_module->wires[wire->name] = wire;
- RTLIL::SigChunk chunk;
- chunk.wire = wire;
- chunk.width = wire->width;
- chunk.offset = 0;
-
- RTLIL::SigSpec sig;
- sig.chunks().push_back(chunk);
- sig.size() = chunk.width;
-
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n",
@@ -175,8 +148,8 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
cell->connections["\\B"] = right;
cell->parameters["\\Y_WIDTH"] = result_width;
- cell->connections["\\Y"] = sig;
- return sig;
+ cell->connections["\\Y"] = wire;
+ return wire;
}
// helper function for creating RTLIL code for multiplexers
@@ -199,15 +172,6 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
wire->width = left.size();
current_module->wires[wire->name] = wire;
- RTLIL::SigChunk chunk;
- chunk.wire = wire;
- chunk.width = wire->width;
- chunk.offset = 0;
-
- RTLIL::SigSpec sig;
- sig.chunks().push_back(chunk);
- sig.size() = chunk.width;
-
for (auto &attr : that->attributes) {
if (attr.second->type != AST_CONSTANT)
log_error("Attribute `%s' with non-constant value at %s:%d!\n",
@@ -220,9 +184,9 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
cell->connections["\\A"] = right;
cell->connections["\\B"] = left;
cell->connections["\\S"] = cond;
- cell->connections["\\Y"] = sig;
+ cell->connections["\\Y"] = wire;
- return sig;
+ return wire;
}
// helper class for converting AST always nodes to RTLIL processes
@@ -1001,9 +965,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
}
}
- RTLIL::SigSpec sig;
- sig.chunks().push_back(chunk);
- sig.size() = chunk.width;
+ RTLIL::SigSpec sig(chunk);
if (genRTLIL_subst_from && genRTLIL_subst_to)
sig.replace(*genRTLIL_subst_from, *genRTLIL_subst_to);
@@ -1025,14 +987,8 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
// concatenation of signals can be done directly using RTLIL::SigSpec
case AST_CONCAT: {
RTLIL::SigSpec sig;
- sig.size() = 0;
- for (auto it = children.begin(); it != children.end(); it++) {
- RTLIL::SigSpec s = (*it)->genRTLIL();
- for (size_t i = 0; i < s.chunks().size(); i++) {
- sig.chunks().push_back(s.chunks()[i]);
- sig.size() += s.chunks()[i].width;
- }
- }
+ for (auto it = children.begin(); it != children.end(); it++)
+ sig.append((*it)->genRTLIL());
if (sig.size() < width_hint)
sig.extend_u0(width_hint, false);
return sig;
diff --git a/frontends/ilang/parser.y b/frontends/ilang/parser.y
index e8af447b..e4d12f3a 100644
--- a/frontends/ilang/parser.y
+++ b/frontends/ilang/parser.y
@@ -357,50 +357,25 @@ constant:
sigspec:
constant {
- RTLIL::SigChunk chunk;
- chunk.wire = NULL;
- chunk.width = $1->bits.size();
- chunk.offset = 0;
- chunk.data = *$1;
- $$ = new RTLIL::SigSpec;
- $$->chunks().push_back(chunk);
- $$->size() = chunk.width;
+ $$ = new RTLIL::SigSpec(*$1);
delete $1;
} |
TOK_ID {
if (current_module->wires.count($1) == 0)
rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
- RTLIL::SigChunk chunk;
- chunk.wire = current_module->wires[$1];
- chunk.width = current_module->wires[$1]->width;
- chunk.offset = 0;
- $$ = new RTLIL::SigSpec;
- $$->chunks().push_back(chunk);
- $$->size() = chunk.width;
+ $$ = new RTLIL::SigSpec(current_module->wires[$1]);
free($1);
} |
TOK_ID '[' TOK_INT ']' {
if (current_module->wires.count($1) == 0)
rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
- RTLIL::SigChunk chunk;
- chunk.wire = current_module->wires[$1];
- chunk.offset = $3;
- chunk.width = 1;
- $$ = new RTLIL::SigSpec;
- $$->chunks().push_back(chunk);
- $$->size() = 1;
+ $$ = new RTLIL::SigSpec(current_module->wires[$1], 1, $3);
free($1);
} |
TOK_ID '[' TOK_INT ':' TOK_INT ']' {
if (current_module->wires.count($1) == 0)
rtlil_frontend_ilang_yyerror(stringf("ilang error: wire %s not found", $1).c_str());
- RTLIL::SigChunk chunk;
- chunk.wire = current_module->wires[$1];
- chunk.width = $3 - $5 + 1;
- chunk.offset = $5;
- $$ = new RTLIL::SigSpec;
- $$->chunks().push_back(chunk);
- $$->size() = chunk.width;
+ $$ = new RTLIL::SigSpec(current_module->wires[$1], $3 - $5 + 1, $5);
free($1);
} |
'{' sigspec_list '}' {
@@ -410,14 +385,8 @@ sigspec:
sigspec_list:
sigspec_list sigspec {
$$ = new RTLIL::SigSpec;
- for (auto it = $2->chunks().begin(); it != $2->chunks().end(); it++) {
- $$->chunks().push_back(*it);
- $$->size() += it->width;
- }
- for (auto it = $1->chunks().begin(); it != $1->chunks().end(); it++) {
- $$->chunks().push_back(*it);
- $$->size() += it->width;
- }
+ $$->append(*$2);
+ $$->append(*$1);
delete $1;
delete $2;
} |
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 88ed2f6a..6bbf6960 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -504,8 +504,7 @@ public:
std::vector<RTLIL::SigChunk> &chunks() { return chunks_; }
const std::vector<RTLIL::SigChunk> &chunks() const { return chunks_; }
- int &size() { return width_; }
- const int &size() const { return width_; }
+ int size() const { return width_; }
SigSpec();
SigSpec(const RTLIL::Const &data);