diff options
| -rw-r--r-- | tests/xsthammer/report.sh | 5 | ||||
| -rw-r--r-- | tests/xsthammer/run-vivado.sh | 5 | ||||
| -rw-r--r-- | tests/xsthammer/xl_cells.v | 6 |
3 files changed, 14 insertions, 2 deletions
diff --git a/tests/xsthammer/report.sh b/tests/xsthammer/report.sh index 86823907..d6ddd862 100644 --- a/tests/xsthammer/report.sh +++ b/tests/xsthammer/report.sh @@ -32,6 +32,11 @@ cat ../../xl_cells.v ../../cy_cells.v > cells.v echo -n > fail_patterns.txt for p in syn_vivado syn_quartus syn_xst syn_yosys rtl; do for q in syn_vivado syn_quartus syn_xst syn_yosys rtl; do + if test -f result.${q}.${p}.txt; then + cp result.${q}.${p}.txt result.${p}.${q}.txt + continue + fi + { echo "read_verilog -DGLBL $p.v" echo "rename $job ${job}_1" diff --git a/tests/xsthammer/run-vivado.sh b/tests/xsthammer/run-vivado.sh index e8f57485..26a287d1 100644 --- a/tests/xsthammer/run-vivado.sh +++ b/tests/xsthammer/run-vivado.sh @@ -12,10 +12,11 @@ set -e mkdir -p vivado vivado_temp/$job cd vivado_temp/$job +sed 's/^module/(* use_dsp48="no" *) module/;' < ../../rtl/$job.v > rtl.v cat > $job.tcl <<- EOT - read_verilog ../../rtl/$job.v + read_verilog rtl.v synth_design -part xc7k70t -top $job - write_verilog ../../vivado/$job.v + write_verilog -force ../../vivado/$job.v EOT /opt/Xilinx/Vivado/2013.2/bin/vivado -mode batch -source $job.tcl diff --git a/tests/xsthammer/xl_cells.v b/tests/xsthammer/xl_cells.v index 3c1e77d2..cfb2102f 100644 --- a/tests/xsthammer/xl_cells.v +++ b/tests/xsthammer/xl_cells.v @@ -88,6 +88,12 @@ output O; assign O = S ? I1 : I0; endmodule +module MUXF8(O, I0, I1, S); +input I0, I1, S; +output O; +assign O = S ? I1 : I0; +endmodule + module VCC(P); output P; assign P = 1; |