diff options
| -rw-r--r-- | manual/PRESENTATION_ExAdv.tex | 40 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/Makefile | 5 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/sym_mul_cells.v | 6 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/sym_mul_map.v | 15 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/sym_mul_test.v | 5 | ||||
| -rw-r--r-- | manual/PRESENTATION_ExAdv/sym_mul_test.ys | 6 |
6 files changed, 74 insertions, 3 deletions
diff --git a/manual/PRESENTATION_ExAdv.tex b/manual/PRESENTATION_ExAdv.tex index 3f5743da..4ef10d7a 100644 --- a/manual/PRESENTATION_ExAdv.tex +++ b/manual/PRESENTATION_ExAdv.tex @@ -259,7 +259,7 @@ Generate blocks and recursion are powerful tools for writing map files. \end{itemize} \end{frame} -\begin{frame}[t]{\subsubsecname -- Example 1/2} +\begin{frame}[t]{\subsubsecname{} -- Example 1/2} \vskip-0.2cm To map the Verilog OR-reduction operator to 3-input OR gates: \vskip-0.2cm @@ -271,7 +271,7 @@ To map the Verilog OR-reduction operator to 3-input OR gates: \end{columns} \end{frame} -\begin{frame}[t]{\subsubsecname -- Example 2/2} +\begin{frame}[t]{\subsubsecname{} -- Example 2/2} \vbox to 0cm{ \hfil\includegraphics[width=10cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/red_or3x1.pdf} \vss @@ -284,6 +284,42 @@ To map the Verilog OR-reduction operator to 3-input OR gates: \end{columns} \end{frame} +\subsubsection{Conditional techmap} + +\begin{frame}{\subsubsecname} +\begin{itemize} +\item In some cases only cells with certain properties should be substituted. +\medskip +\item The special wire {\tt \_TECHMAP\_FAIL\_} can be used to disable a module +in the map file for a certain set of parameters. +\medskip +\item The wire {\tt \_TECHMAP\_FAIL\_} must be set to a constant value. If it +is non-zero then the module is disabled for this set of parameters. +\medskip +\item Example use-cases: +\begin{itemize} +\item coarse-grain cell types that only operate on certain bit widths +\item memory resources for different memory geometries (width, depth, ports, etc.) +\end{itemize} +\end{itemize} +\end{frame} + +\begin{frame}[t]{\subsubsecname{} -- Example} +\vbox to 0cm{ +\vskip-0.5cm +\hfill\includegraphics[width=6cm,trim=0 0cm 0 0cm]{PRESENTATION_ExAdv/sym_mul.pdf} +\vss +} +\vskip-0.5cm +\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, language=verilog]{PRESENTATION_ExAdv/sym_mul_map.v} +\begin{columns} +\column[t]{6cm} +\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=verilog]{PRESENTATION_ExAdv/sym_mul_test.v} +\column[t]{4cm} +\vskip-0.5cm\lstinputlisting[basicstyle=\ttfamily\fontsize{8pt}{10pt}\selectfont, frame=single, language=ys, lastline=4]{PRESENTATION_ExAdv/sym_mul_test.ys} +\end{columns} +\end{frame} + \subsubsection{TBD} \begin{frame}{\subsubsecname} diff --git a/manual/PRESENTATION_ExAdv/Makefile b/manual/PRESENTATION_ExAdv/Makefile index 673b3a21..4ee5886d 100644 --- a/manual/PRESENTATION_ExAdv/Makefile +++ b/manual/PRESENTATION_ExAdv/Makefile @@ -1,5 +1,5 @@ -all: select_01.pdf red_or3x1.pdf +all: select_01.pdf red_or3x1.pdf sym_mul.pdf select_01.pdf: select_01.v select_01.ys ../../yosys select_01.ys @@ -7,3 +7,6 @@ select_01.pdf: select_01.v select_01.ys red_or3x1.pdf: red_or3x1_* ../../yosys red_or3x1_test.ys +sym_mul.pdf: sym_mul_* + ../../yosys sym_mul_test.ys + diff --git a/manual/PRESENTATION_ExAdv/sym_mul_cells.v b/manual/PRESENTATION_ExAdv/sym_mul_cells.v new file mode 100644 index 00000000..ce177154 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/sym_mul_cells.v @@ -0,0 +1,6 @@ +module MYMUL(A, B, Y); + parameter WIDTH = 1; + input [WIDTH-1:0] A, B; + output [WIDTH-1:0] Y; + assign Y = A * B; +endmodule diff --git a/manual/PRESENTATION_ExAdv/sym_mul_map.v b/manual/PRESENTATION_ExAdv/sym_mul_map.v new file mode 100644 index 00000000..293c5b84 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/sym_mul_map.v @@ -0,0 +1,15 @@ +module \$mul (A, B, Y); + parameter A_SIGNED = 0; + parameter B_SIGNED = 0; + parameter A_WIDTH = 1; + parameter B_WIDTH = 1; + parameter Y_WIDTH = 1; + + input [A_WIDTH-1:0] A; + input [B_WIDTH-1:0] B; + output [Y_WIDTH-1:0] Y; + + wire _TECHMAP_FAIL_ = A_WIDTH != B_WIDTH || B_WIDTH != Y_WIDTH; + + MYMUL #( .WIDTH(Y_WIDTH) ) g ( .A(A), .B(B), .Y(Y) ); +endmodule diff --git a/manual/PRESENTATION_ExAdv/sym_mul_test.v b/manual/PRESENTATION_ExAdv/sym_mul_test.v new file mode 100644 index 00000000..eb715f83 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/sym_mul_test.v @@ -0,0 +1,5 @@ +module test(A, B, C, Y1, Y2); + input [7:0] A, B, C; + output [7:0] Y1 = A * B; + output [15:0] Y2 = A * C; +endmodule diff --git a/manual/PRESENTATION_ExAdv/sym_mul_test.ys b/manual/PRESENTATION_ExAdv/sym_mul_test.ys new file mode 100644 index 00000000..0c07e7e8 --- /dev/null +++ b/manual/PRESENTATION_ExAdv/sym_mul_test.ys @@ -0,0 +1,6 @@ +read_verilog sym_mul_test.v +hierarchy -check -top test + +techmap -map sym_mul_map.v;; + +show -prefix sym_mul -format pdf -notitle -lib sym_mul_cells.v |