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-rw-r--r--passes/hierarchy/hierarchy.cc4
1 files changed, 2 insertions, 2 deletions
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 028a0f0c..e95947a9 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -206,9 +206,9 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
for (auto &conn : cell->connections())
if (conn.first[0] == '$' && '0' <= conn.first[1] && conn.first[1] <= '9') {
int id = atoi(conn.first.c_str()+1);
- if (id < 0 || id >= GetSize(mod->ports))
+ if (id <= 0 || id > GetSize(mod->ports))
log_error("Module `%s' referenced in module `%s' in cell `%s' has only %d ports, requested port %d.\n",
- log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id + 1);
+ log_id(cell->type), log_id(module), log_id(cell), GetSize(mod->ports), id);
} else if (mod->wire(conn.first) == nullptr || mod->wire(conn.first)->port_id == 0)
log_error("Module `%s' referenced in module `%s' in cell `%s' does not have a port named '%s'.\n",
log_id(cell->type), log_id(module), log_id(cell), log_id(conn.first));