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-rw-r--r--kernel/calc.cc5
-rw-r--r--kernel/satgen.h7
-rw-r--r--techlibs/common/simlib.v5
3 files changed, 8 insertions, 9 deletions
diff --git a/kernel/calc.cc b/kernel/calc.cc
index 7bfdb895..4048e4a1 100644
--- a/kernel/calc.cc
+++ b/kernel/calc.cc
@@ -591,10 +591,9 @@ RTLIL::Const RTLIL::const_bu0(const RTLIL::Const &arg1, const RTLIL::Const&, boo
RTLIL::Const RTLIL::const_neg(const RTLIL::Const &arg1, const RTLIL::Const&, bool signed1, bool, int result_len)
{
RTLIL::Const arg1_ext = arg1;
- extend(arg1_ext, result_len, signed1);
-
RTLIL::Const zero(RTLIL::State::S0, 1);
- return RTLIL::const_sub(zero, arg1_ext, false, signed1, result_len);
+
+ return RTLIL::const_sub(zero, arg1_ext, true, signed1, result_len);
}
YOSYS_NAMESPACE_END
diff --git a/kernel/satgen.h b/kernel/satgen.h
index beb03768..3685cd6e 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -357,7 +357,7 @@ struct SatGen
if (model_undef) {
std::vector<int> undef_a = importUndefSigSpec(cell->getPort("\\A"), timestep);
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
- extendSignalWidthUnary(undef_a, undef_y, cell, true);
+ extendSignalWidthUnary(undef_a, undef_y, cell, false);
ez->assume(ez->vec_eq(undef_a, undef_y));
undefGating(y, yy, undef_y);
}
@@ -671,7 +671,7 @@ struct SatGen
int extend_bit = ez->FALSE;
- if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool())
+ if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool())
extend_bit = a.back();
while (y.size() < a.size())
@@ -703,7 +703,8 @@ struct SatGen
std::vector<int> undef_y = importUndefSigSpec(cell->getPort("\\Y"), timestep);
std::vector<int> undef_a_shifted;
- if (cell->type != "$shift" && cell->type != "$shiftx" && cell->parameters["\\A_SIGNED"].as_bool())
+ extend_bit = cell->type == "$shiftx" ? ez->TRUE : ez->FALSE;
+ if (!cell->type.in("$shift", "$shiftx") && cell->parameters["\\A_SIGNED"].as_bool())
extend_bit = undef_a.back();
while (undef_y.size() < undef_a.size())
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 3c931c81..09ffa9a6 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -108,13 +108,12 @@ parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
output [Y_WIDTH-1:0] Y;
-wire [Y_WIDTH-1:0] tmp;
generate
if (A_SIGNED) begin:BLOCK1
- assign tmp = $signed(A), Y = -tmp;
+ assign Y = -$signed(A);
end else begin:BLOCK2
- assign tmp = A, Y = -tmp;
+ assign Y = -A;
end
endgenerate