diff options
| -rw-r--r-- | kernel/celltypes.h | 3 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 1 | ||||
| -rw-r--r-- | passes/abc/abc.cc | 10 | ||||
| -rw-r--r-- | passes/opt/opt_clean.cc | 4 | ||||
| -rw-r--r-- | techlibs/common/simcells.v | 6 |
5 files changed, 19 insertions, 5 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 85c21ef3..2774073d 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -130,6 +130,7 @@ struct CellTypes void setup_stdcells() { + setup_type("$_BUF_", {"\\A"}, {"\\Y"}, true); setup_type("$_NOT_", {"\\A"}, {"\\Y"}, true); setup_type("$_AND_", {"\\A", "\\B"}, {"\\Y"}, true); setup_type("$_NAND_", {"\\A", "\\B"}, {"\\Y"}, true); @@ -261,6 +262,8 @@ struct CellTypes HANDLE_CELL_TYPE(neg) #undef HANDLE_CELL_TYPE + if (type == "$_BUF_") + return arg1; if (type == "$_NOT_") return eval_not(arg1); if (type == "$_AND_") diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 00be796f..89132ea2 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -870,6 +870,7 @@ namespace { return; } + if (cell->type == "$_BUF_") { check_gate("AY"); return; } if (cell->type == "$_NOT_") { check_gate("AY"); return; } if (cell->type == "$_AND_") { check_gate("ABY"); return; } if (cell->type == "$_NAND_") { check_gate("ABY"); return; } diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 1a7de066..3e105411 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -59,6 +59,7 @@ PRIVATE_NAMESPACE_BEGIN enum class gate_type_t { G_NONE, G_FF, + G_BUF, G_NOT, G_AND, G_NAND, @@ -160,7 +161,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) return; } - if (cell->type == "$_NOT_") + if (cell->type.in("$_BUF_", "$_NOT_")) { RTLIL::SigSpec sig_a = cell->getPort("\\A"); RTLIL::SigSpec sig_y = cell->getPort("\\Y"); @@ -168,7 +169,7 @@ static void extract_cell(RTLIL::Cell *cell, bool keepff) assign_map.apply(sig_a); assign_map.apply(sig_y); - map_signal(sig_y, G(NOT), map_signal(sig_a)); + map_signal(sig_y, cell->type == "$_BUF_" ? G(BUF) : G(NOT), map_signal(sig_a)); module->remove(cell); return; @@ -645,7 +646,10 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std int count_gates = 0; for (auto &si : signal_list) { - if (si.type == G(NOT)) { + if (si.type == G(BUF)) { + fprintf(f, ".names n%d n%d\n", si.in1, si.id); + fprintf(f, "1 1\n"); + } else if (si.type == G(NOT)) { fprintf(f, ".names n%d n%d\n", si.in1, si.id); fprintf(f, "0 1\n"); } else if (si.type == G(AND)) { diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc index 15bbf54e..004a2078 100644 --- a/passes/opt/opt_clean.cc +++ b/passes/opt/opt_clean.cc @@ -295,8 +295,8 @@ void rmunused_module(RTLIL::Module *module, bool purge_mode, bool verbose) std::vector<RTLIL::Cell*> delcells; for (auto cell : module->cells()) - if (cell->type == "$pos") { - bool is_signed = cell->getParam("\\A_SIGNED").as_bool(); + if (cell->type.in("$pos", "$_BUF_")) { + bool is_signed = cell->type == "$pos" && cell->getParam("\\A_SIGNED").as_bool(); RTLIL::SigSpec a = cell->getPort("\\A"); RTLIL::SigSpec y = cell->getPort("\\Y"); a.extend_u0(SIZE(y), is_signed); diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index a2a37735..88566411 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -25,6 +25,12 @@ * */ +module \$_BUF_ (A, Y); +input A; +output Y; +assign Y = A; +endmodule + module \$_NOT_ (A, Y); input A; output Y; |