1 files changed, 4 insertions, 0 deletions
@@ -367,6 +367,10 @@ Verilog Attributes and non-standard features
expressions as <size>. If the expression is not a simple identifier, it
must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
+- The system tasks $finish and $display are supported in initial blocks
+ in and unconditional context (only if/case statements on parameters
+ and constant values). The intended use for this is synthesis-time DRC.
Supported features from SystemVerilog