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-rw-r--r--README4
1 files changed, 4 insertions, 0 deletions
diff --git a/README b/README
index 0a1c2068..868fd90e 100644
--- a/README
+++ b/README
@@ -367,6 +367,10 @@ Verilog Attributes and non-standard features
expressions as <size>. If the expression is not a simple identifier, it
must be put in parentheses. Examples: WIDTH'd42, (4+2)'b101010
+- The system tasks $finish and $display are supported in initial blocks
+ in and unconditional context (only if/case statements on parameters
+ and constant values). The intended use for this is synthesis-time DRC.
+
Supported features from SystemVerilog
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