**diff options**

-rw-r--r-- | kernel/driver.cc | 2 | ||||

-rw-r--r-- | kernel/select.cc | 12 | ||||

-rw-r--r-- | kernel/show.cc | 2 | ||||

-rw-r--r-- | passes/abc/abc.cc | 6 | ||||

-rw-r--r-- | passes/fsm/fsm_detect.cc | 6 | ||||

-rw-r--r-- | passes/fsm/fsm_expand.cc | 2 | ||||

-rw-r--r-- | passes/opt/opt_muxtree.cc | 2 | ||||

-rw-r--r-- | passes/opt/opt_rmunused.cc | 6 | ||||

-rw-r--r-- | passes/proc/proc_dff.cc | 4 | ||||

-rw-r--r-- | passes/scc/scc.cc | 2 | ||||

-rw-r--r-- | passes/submod/submod.cc | 4 | ||||

-rw-r--r-- | passes/techmap/techmap.cc | 4 |

12 files changed, 26 insertions, 26 deletions

diff --git a/kernel/driver.cc b/kernel/driver.cc index 0da5f68c..bc605a46 100644 --- a/kernel/driver.cc +++ b/kernel/driver.cc @@ -205,7 +205,7 @@ struct ShellPass : public Pass { log(" yosys [modname]*>\n"); log(" only part of current module 'modname' is selected\n"); log("\n"); - log("When in interavtive shell, some errors (e.g. invalid command arguments)\n"); + log("When in interactive shell, some errors (e.g. invalid command arguments)\n"); log("do not terminate yosys but return to the command prompt.\n"); log("\n"); log("This command is the default action if nothing else has been specified\n"); diff --git a/kernel/select.cc b/kernel/select.cc index 3c6fd669..a6e675c8 100644 --- a/kernel/select.cc +++ b/kernel/select.cc @@ -642,13 +642,13 @@ struct SelectPass : public Pass { log(" whole design.\n"); log("\n"); log(" -module <modname>\n"); - log(" limit the current scope to the specified module\n"); + log(" limit the current scope to the specified module.\n"); log(" the difference between this and simply selecting the module\n"); log(" is that all object names are interpreted relative to this\n"); log(" module after this command until the selection is cleared again.\n"); log("\n"); log("When this command is called without an argument, the current selection\n"); - log("is displayed in a compact form (i.e.. only the module name when a whole module\n"); + log("is displayed in a compact form (i.e. only the module name when a whole module\n"); log("is selected).\n"); log("\n"); log("The <selection> argument itself is a series of commands for a simple stack\n"); @@ -697,8 +697,8 @@ struct SelectPass : public Pass { log(" all objects with a matching attribute name-value-pair\n"); log("\n"); log(" n:<pattern>\n"); - log(" all object with a name matching the given pattern\n"); - log(" (i.e. the n: is optional as it is the default matching rule)\n"); + log(" all objects with a name matching the given pattern\n"); + log(" (i.e. 'n:' is optional as it is the default matching rule)\n"); log("\n"); log(" @<name>\n"); log(" push the selection saved prior with 'select -set <name> ...'\n"); @@ -724,12 +724,12 @@ struct SelectPass : public Pass { log(" pop the top set from the stack and subtract it from the new top\n"); log("\n"); log(" %%x[<num1>|*][.<num2>][:<rule>[:<rule>..]]\n"); - log(" expand top set <num1> num times accorind to the specified rules.\n"); + log(" expand top set <num1> num times according to the specified rules.\n"); log(" (i.e. select all cells connected to selected wires and select all\n"); log(" wires connected to selected cells) The rules specify which cell\n"); log(" ports to use for this. the syntax for a rule is a '-' for exclusion\n"); log(" and a '+' for inclusion, followed by an optional comma seperated\n"); - log(" list of cell types followed by an optional comma seperated list of\n"); + log(" list of cell types followed by an optional comma separated list of\n"); log(" cell ports in square brackets. a rule can also be just a cell or wire\n"); log(" name that limits the expansion (is included but does not go beyond).\n"); log(" select at most <num2> objects. a warning message is printed when this\n"); diff --git a/kernel/show.cc b/kernel/show.cc index c556c991..50cddce9 100644 --- a/kernel/show.cc +++ b/kernel/show.cc @@ -319,7 +319,7 @@ struct ShowPass : public Pass { log(" Also run the specified command with the postscript file as parameter.\n"); log("\n"); log(" -lib <verilog_or_ilang_file>\n"); - log(" Use the specified library file for determining whether cell ports are.\n"); + log(" Use the specified library file for determining whether cell ports are\n"); log(" inputs or outputs. This option can be used multiple times to specify\n"); log(" more than one library.\n"); log("\n"); diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc index 4196cac8..b7680f06 100644 --- a/passes/abc/abc.cc +++ b/passes/abc/abc.cc @@ -638,9 +638,9 @@ struct AbcPass : public Pass { log("\n"); log(" -liberty <file>\n"); log(" generate netlists for the specified cell library (using the liberty\n"); - log(" file format). This option is ignored if also -script option is also\n"); - log(" used. Without this option, ABC is used to optimize the netlist but\n"); - log(" keeps using yosys's internal gate library.\n"); + log(" file format). Without this option, ABC is used to optimize the netlist\n"); + log(" but keeps using yosys's internal gate library. This option is ignored if\n"); + log(" the -script option is also used.\n"); log("\n"); log(" -nocleanup\n"); log(" when this option is used, the temporary files created by this pass\n"); diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc index f20675ff..e1cef943 100644 --- a/passes/fsm/fsm_detect.cc +++ b/passes/fsm/fsm_detect.cc @@ -116,14 +116,14 @@ struct FsmDetectPass : public Pass { log("\n"); log(" fsm_detect [selection]\n"); log("\n"); - log("This pass detects finite state machine by identifying the state signal.\n"); + log("This pass detects finite state machines by identifying the state signal.\n"); log("The state signal is then marked by setting the attribute 'fsm_encoding'\n"); log("on the state signal to \"auto\".\n"); log("\n"); log("Existing 'fsm_encoding' attributes are not changed by this pass.\n"); log("\n"); - log("Signals can be protected from beeing detected by this pass by setting the\n"); - log("'fsm_encoding' atrribute to \"none\".\n"); + log("Signals can be protected from being detected by this pass by setting the\n"); + log("'fsm_encoding' attribute to \"none\".\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) diff --git a/passes/fsm/fsm_expand.cc b/passes/fsm/fsm_expand.cc index e6829f49..df3aec85 100644 --- a/passes/fsm/fsm_expand.cc +++ b/passes/fsm/fsm_expand.cc @@ -241,7 +241,7 @@ struct FsmExpandPass : public Pass { log("\n"); log(" fsm_expand [selection]\n"); log("\n"); - log("The fsm_extract pass is conservative about the cells that belong the a finate\n"); + log("The fsm_extract pass is conservative about the cells that belong to a finite\n"); log("state machine. This pass can be used to merge additional auxiliary gates into\n"); log("the finate state machine.\n"); log("\n"); diff --git a/passes/opt/opt_muxtree.cc b/passes/opt/opt_muxtree.cc index 5602b5ee..49b72f15 100644 --- a/passes/opt/opt_muxtree.cc +++ b/passes/opt/opt_muxtree.cc @@ -406,7 +406,7 @@ struct OptMuxtreePass : public Pass { log(" opt_muxtree [selection]\n"); log("\n"); log("This pass analyzes the control signals for the multiplexer trees in the design\n"); - log("and identifies inputs that can never be active. In then removes this dead\n"); + log("and identifies inputs that can never be active. It then removes this dead\n"); log("branches from the multiplexer trees.\n"); log("\n"); log("This pass only operates on completely selected modules without processes.\n"); diff --git a/passes/opt/opt_rmunused.cc b/passes/opt/opt_rmunused.cc index c72a4587..6cec9b29 100644 --- a/passes/opt/opt_rmunused.cc +++ b/passes/opt/opt_rmunused.cc @@ -242,9 +242,9 @@ struct OptRmUnusedPass : public Pass { log(" opt_rmunused [selection]\n"); log("\n"); log("This pass identifies wires and cells that are unused and removes them. Other\n"); - log("often remove cells but leave the wires in the design or reconnect the wires\n"); - log("but leave the old cells in the design. This pass can be used to clean up after\n"); - log("the passes that do the actual work.\n"); + log("passes often remove cells but leave the wires in the design or reconnect the\n"); + log("wires but leave the old cells in the design. This pass can be used to clean up\n"); + log("after the passes that do the actual work.\n"); log("\n"); log("This pass only operates on completely selected modules without processes.\n"); log("\n"); diff --git a/passes/proc/proc_dff.cc b/passes/proc/proc_dff.cc index 93b90006..94827c12 100644 --- a/passes/proc/proc_dff.cc +++ b/passes/proc/proc_dff.cc @@ -168,8 +168,8 @@ struct ProcDffPass : public Pass { log("\n"); log(" proc_dff [selection]\n"); log("\n"); - log("This pass identifies flip-flops in the processes and converts then to\n"); - log("flip-flop cells.\n"); + log("This pass identifies flip-flops in the processes and converts them to\n"); + log("d-type flip-flop cells.\n"); log("\n"); } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) diff --git a/passes/scc/scc.cc b/passes/scc/scc.cc index 0dde3cbe..f8c351a4 100644 --- a/passes/scc/scc.cc +++ b/passes/scc/scc.cc @@ -211,7 +211,7 @@ struct SccPass : public Pass { log("\n"); log(" -max_depth <num>\n"); log(" limit to loops not longer than the specified number of cells. This can\n"); - log(" e.g. be usefull in identifying local loops in a module that turns out\n"); + log(" e.g. be useful in identifying local loops in a module that turns out\n"); log(" to be one gigantic SCC.\n"); log("\n"); log(" -all_cell_types\n"); diff --git a/passes/submod/submod.cc b/passes/submod/submod.cc index f30e415b..f91d1ec3 100644 --- a/passes/submod/submod.cc +++ b/passes/submod/submod.cc @@ -239,7 +239,7 @@ struct SubmodWorker }; struct SubmodPass : public Pass { - SubmodPass() : Pass("submod", "moving part of a module to a new submodle") { } + SubmodPass() : Pass("submod", "moving part of a module to a new submodule") { } virtual void help() { // |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---| @@ -259,7 +259,7 @@ struct SubmodPass : public Pass { } virtual void execute(std::vector<std::string> args, RTLIL::Design *design) { - log_header("Executing SUBMOD pass (moving cells to submodes as requested).\n"); + log_header("Executing SUBMOD pass (moving cells to submodules as requested).\n"); log_push(); Pass::call(design, "opt_rmunused"); diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc index c05a96cd..5fd5858a 100644 --- a/passes/techmap/techmap.cc +++ b/passes/techmap/techmap.cc @@ -172,14 +172,14 @@ struct TechmapPass : public Pass { log("\n"); log(" techmap [-map filename] [selection]\n"); log("\n"); - log("This pass implements a very simple technology mapper than replaces cells in\n"); + log("This pass implements a very simple technology mapper that replaces cells in\n"); log("the design with implementations given in form of a verilog or ilang source\n"); log("file.\n"); log("\n"); log(" -map filename\n"); log(" the library of cell implementations to be used.\n"); log(" without this parameter a builtin library is used that\n"); - log(" transform the internal RTL cells to the internal gate\n"); + log(" transforms the internal RTL cells to the internal gate\n"); log(" library.\n"); log("\n"); log("See 'help extract' for a pass that does the opposite thing.\n"); |