diff options
| -rw-r--r-- | techlibs/xilinx/brams.v | 28 |
1 files changed, 14 insertions, 14 deletions
diff --git a/techlibs/xilinx/brams.v b/techlibs/xilinx/brams.v index 83f2aede..d9d5391b 100644 --- a/techlibs/xilinx/brams.v +++ b/techlibs/xilinx/brams.v @@ -50,8 +50,8 @@ module \$__XILINX_RAMB36_SDP72 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN .RAM_MODE("SDP"), .READ_WIDTH_A(72), .WRITE_WIDTH_B(72), - .WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"), - .WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST") + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST") ) _TECHMAP_REPLACE_ ( .DOBDO(DO[63:32]), .DOADO(DO[31:0]), @@ -127,8 +127,8 @@ module \$__XILINX_RAMB18_SDP36 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN .RAM_MODE("SDP"), .READ_WIDTH_A(36), .WRITE_WIDTH_B(36), - .WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"), - .WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST") + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST") ) _TECHMAP_REPLACE_ ( .DOBDO(DO[31:16]), .DOADO(DO[15:0]), @@ -204,8 +204,8 @@ module \$__XILINX_RAMB18_TDP18 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN .READ_WIDTH_B(18), .WRITE_WIDTH_A(18), .WRITE_WIDTH_B(18), - .WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"), - .WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST") + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST") ) _TECHMAP_REPLACE_ ( .DIADI(16'b0), .DIPADIP(2'b0), @@ -277,8 +277,8 @@ module \$__XILINX_RAMB18_TDP9 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN) .READ_WIDTH_B(9), .WRITE_WIDTH_A(9), .WRITE_WIDTH_B(9), - .WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"), - .WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST") + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST") ) _TECHMAP_REPLACE_ ( .DIADI(16'b0), .DIPADIP(2'b0), @@ -350,8 +350,8 @@ module \$__XILINX_RAMB18_TDP4 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN) .READ_WIDTH_B(4), .WRITE_WIDTH_A(4), .WRITE_WIDTH_B(4), - .WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"), - .WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST") + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST") ) _TECHMAP_REPLACE_ ( .DIADI(16'b0), .DIPADIP(2'b0), @@ -423,8 +423,8 @@ module \$__XILINX_RAMB18_TDP2 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN) .READ_WIDTH_B(2), .WRITE_WIDTH_A(2), .WRITE_WIDTH_B(2), - .WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"), - .WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST") + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST") ) _TECHMAP_REPLACE_ ( .DIADI(16'b0), .DIPADIP(2'b0), @@ -496,8 +496,8 @@ module \$__XILINX_RAMB18_TDP1 (CLK2, CLK3, A1ADDR, A1DATA, B1ADDR, B1DATA, B1EN) .READ_WIDTH_B(1), .WRITE_WIDTH_A(1), .WRITE_WIDTH_B(1), - .WRITE_MODE_A(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST"), - .WRITE_MODE_B(TRANSP2 ? "WRITE_FIRST" : "READ_FIRST") + .WRITE_MODE_A("READ_FIRST"), + .WRITE_MODE_B("READ_FIRST") ) _TECHMAP_REPLACE_ ( .DIADI(16'b0), .DIPADIP(2'b0), |