diff options
| -rw-r--r-- | frontends/verilog/parser.y | 7 | ||||
| -rw-r--r-- | tests/simple/macros.v | 7 |
2 files changed, 14 insertions, 0 deletions
diff --git a/frontends/verilog/parser.y b/frontends/verilog/parser.y index 37c3232a..ce7b9927 100644 --- a/frontends/verilog/parser.y +++ b/frontends/verilog/parser.y @@ -1140,6 +1140,13 @@ basic_expr: delete $1; delete $2; } | + TOK_CONST TOK_CONST { + $$ = const2ast(*$1 + *$2, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); + if ($$ == NULL || (*$2)[0] != '\'') + log_error("Value conversion failed: `%s%s'\n", $1->c_str(), $2->c_str()); + delete $1; + delete $2; + } | TOK_CONST { $$ = const2ast(*$1, case_type_stack.size() == 0 ? 0 : case_type_stack.back()); if ($$ == NULL) diff --git a/tests/simple/macros.v b/tests/simple/macros.v index cda46cb4..a3e8d70f 100644 --- a/tests/simple/macros.v +++ b/tests/simple/macros.v @@ -235,3 +235,10 @@ always @* begin end endmodule + +`define SIZE 4 // comment supported in this part +module test ( din_a, dout_a ); +input [`SIZE-1:0] din_a; +output [`SIZE-1:0] dout_a; +assign dout_a = din_a | `SIZE'ha; +endmodule |