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-rw-r--r--backends/intersynth/intersynth.cc9
-rw-r--r--passes/extract/extract.cc42
-rw-r--r--passes/techmap/libparse.cc5
3 files changed, 39 insertions, 17 deletions
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index 402c3e7c..47c1125f 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -149,8 +149,10 @@ struct IntersynthBackend : public Backend {
log_error("Can't generate a netlist for a module with unprocessed memories or processes!\n");
std::set<std::string> constcells_code;
+ netlists_code += stringf("# Netlist of module %s\n", RTLIL::id2cstr(module->name));
netlists_code += stringf("netlist %s\n", RTLIL::id2cstr(module->name));
+ // Module Ports: "std::set<string> celltypes_code" prevents duplicate top level ports
for (auto wire_it : module->wires) {
RTLIL::Wire *wire = wire_it.second;
if (wire->port_input || wire->port_output) {
@@ -162,6 +164,7 @@ struct IntersynthBackend : public Backend {
}
}
+ // Submodules: "std::set<string> celltypes_code" prevents duplicate cell types
for (auto cell_it : module->cells)
{
RTLIL::Cell *cell = cell_it.second;
@@ -194,16 +197,22 @@ struct IntersynthBackend : public Backend {
netlists_code += node_code + "\n";
}
+ if (constcells_code.size() > 0)
+ netlists_code += "# constant cells\n";
for (auto code : constcells_code)
netlists_code += code;
+ netlists_code += "\n";
}
if (!flag_notypes) {
+ fprintf(f, "### Connection Types\n");
for (auto code : conntypes_code)
fprintf(f, "%s", code.c_str());
+ fprintf(f, "\n### Cell Types\n");
for (auto code : celltypes_code)
fprintf(f, "%s", code.c_str());
}
+ fprintf(f, "\n### Netlists\n");
fprintf(f, "%s", netlists_code.c_str());
for (auto lib : libs)
diff --git a/passes/extract/extract.cc b/passes/extract/extract.cc
index aa21e573..eff14ff0 100644
--- a/passes/extract/extract.cc
+++ b/passes/extract/extract.cc
@@ -312,7 +312,8 @@ struct ExtractPass : public Pass {
log("map file can be a verilog source file (*.v) or an ilang file (*.il).\n");
log("\n");
log(" -map <map_file>\n");
- log(" use the modules in this file as reference\n");
+ log(" use the modules in this file as reference. This option can be used\n");
+ log(" multiple times.\n");
log("\n");
log(" -verbose\n");
log(" print debug output while analyzing\n");
@@ -384,7 +385,8 @@ struct ExtractPass : public Pass {
SubCircuitSolver solver;
- std::string filename;
+ std::vector<std::string> map_filenames;
+ std::string mine_outfile;
bool constports = false;
bool nodefaultswaps = false;
@@ -399,11 +401,15 @@ struct ExtractPass : public Pass {
size_t argidx;
for (argidx = 1; argidx < args.size(); argidx++) {
if (args[argidx] == "-map" && argidx+1 < args.size()) {
- filename = args[++argidx];
+ if (mine_mode)
+ log_cmd_error("You cannot mix -map and -mine.\n");
+ map_filenames.push_back(args[++argidx]);
continue;
}
if (args[argidx] == "-mine" && argidx+1 < args.size()) {
- filename = args[++argidx];
+ if (!map_filenames.empty())
+ log_cmd_error("You cannot mix -map and -mine.\n");
+ mine_outfile = args[++argidx];
mine_mode = true;
continue;
}
@@ -510,23 +516,25 @@ struct ExtractPass : public Pass {
solver.addSwappablePorts("$_XOR_", "\\A", "\\B");
}
- if (filename.empty())
+ if (map_filenames.empty() && mine_outfile.empty())
log_cmd_error("Missing option -map <verilog_or_ilang_file> or -mine <output_ilang_file>.\n");
RTLIL::Design *map = NULL;
if (!mine_mode)
{
- FILE *f = fopen(filename.c_str(), "rt");
- if (f == NULL)
- log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
map = new RTLIL::Design;
- Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
- fclose(f);
-
- if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") {
- Pass::call(map, "proc");
- Pass::call(map, "opt_clean");
+ for (auto &filename : map_filenames) {
+ FILE *f = fopen(filename.c_str(), "rt");
+ if (f == NULL)
+ log_cmd_error("Can't open map file `%s'.\n", filename.c_str());
+ Frontend::frontend_call(map, f, filename, (filename.size() > 3 && filename.substr(filename.size()-3) == ".il") ? "ilang" : "verilog");
+ fclose(f);
+
+ if (filename.size() <= 3 || filename.substr(filename.size()-3) != ".il") {
+ Pass::call(map, "proc");
+ Pass::call(map, "opt_clean");
+ }
}
}
@@ -658,10 +666,10 @@ struct ExtractPass : public Pass {
}
}
- FILE *f = fopen(filename.c_str(), "wt");
+ FILE *f = fopen(mine_outfile.c_str(), "wt");
if (f == NULL)
- log_error("Can't open output file `%s'.\n", filename.c_str());
- Backend::backend_call(map, f, filename, "ilang");
+ log_error("Can't open output file `%s'.\n", mine_outfile.c_str());
+ Backend::backend_call(map, f, mine_outfile, "ilang");
fclose(f);
}
diff --git a/passes/techmap/libparse.cc b/passes/techmap/libparse.cc
index 8f4a1a5f..8cbb8e2b 100644
--- a/passes/techmap/libparse.cc
+++ b/passes/techmap/libparse.cc
@@ -126,6 +126,11 @@ int LibertyParser::lexer(std::string &str)
line++;
}
return lexer(str);
+ } else if (c == '/') {
+ while (c > 0 && c != '\n')
+ c = fgetc(f);
+ line++;
+ return lexer(str);
}
ungetc(c, f);
// fprintf(stderr, "LEX: char >>/<<\n");