diff options
| -rw-r--r-- | kernel/celltypes.h | 4 | ||||
| -rw-r--r-- | kernel/rtlil.cc | 5 | ||||
| -rw-r--r-- | techlibs/common/simcells.v | 32 |
3 files changed, 41 insertions, 0 deletions
diff --git a/kernel/celltypes.h b/kernel/celltypes.h index 3d9e4cf9..f58ae14c 100644 --- a/kernel/celltypes.h +++ b/kernel/celltypes.h @@ -158,6 +158,10 @@ struct CellTypes for (auto c1 : list_np) for (auto c2 : list_np) + setup_type(stringf("$_DFFE_%c%c_", c1, c2), {"\\C", "\\D", "\\E"}, {"\\Q"}); + + for (auto c1 : list_np) + for (auto c2 : list_np) for (auto c3 : list_01) setup_type(stringf("$_DFF_%c%c%c_", c1, c2, c3), {"\\C", "\\R", "\\D"}, {"\\Q"}); diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 803d783a..321c39e1 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -892,6 +892,11 @@ namespace { if (cell->type == "$_DFF_N_") { check_gate("DQC"); return; } if (cell->type == "$_DFF_P_") { check_gate("DQC"); return; } + if (cell->type == "$_DFFE_NN_") { check_gate("DQCE"); return; } + if (cell->type == "$_DFFE_NP_") { check_gate("DQCE"); return; } + if (cell->type == "$_DFFE_PN_") { check_gate("DQCE"); return; } + if (cell->type == "$_DFFE_PP_") { check_gate("DQCE"); return; } + if (cell->type == "$_DFF_NN0_") { check_gate("DQCR"); return; } if (cell->type == "$_DFF_NN1_") { check_gate("DQCR"); return; } if (cell->type == "$_DFF_NP0_") { check_gate("DQCR"); return; } diff --git a/techlibs/common/simcells.v b/techlibs/common/simcells.v index 88566411..eb62d783 100644 --- a/techlibs/common/simcells.v +++ b/techlibs/common/simcells.v @@ -163,6 +163,38 @@ always @(posedge C) begin end endmodule +module \$_DFFE_NN_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(negedge C) begin + if (!E) Q <= D; +end +endmodule + +module \$_DFFE_NP_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(negedge C) begin + if (E) Q <= D; +end +endmodule + +module \$_DFFE_PN_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(posedge C) begin + if (!E) Q <= D; +end +endmodule + +module \$_DFFE_PP_ (D, Q, C, E); +input D, C, E; +output reg Q; +always @(posedge C) begin + if (E) Q <= D; +end +endmodule + module \$_DFF_NN0_ (D, Q, C, R); input D, C, R; output reg Q; |