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-rw-r--r--backends/verilog/verilog_backend.cc22
-rw-r--r--kernel/celltypes.h19
-rw-r--r--kernel/rtlil.cc18
-rw-r--r--kernel/satgen.h21
-rw-r--r--manual/CHAPTER_CellLib.tex4
-rw-r--r--passes/techmap/simplemap.cc18
-rw-r--r--techlibs/common/simlib.v30
-rw-r--r--techlibs/common/stdcells.v12
8 files changed, 140 insertions, 4 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index d8160c97..d7fe4c4e 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -571,6 +571,28 @@ bool dump_cell_expr(FILE *f, std::string indent, RTLIL::Cell *cell)
return true;
}
+ if (cell->type == "$slice")
+ {
+ fprintf(f, "%s" "assign ", indent.c_str());
+ dump_sigspec(f, cell->connections["\\Y"]);
+ fprintf(f, " = ");
+ dump_sigspec(f, cell->connections["\\A"]);
+ fprintf(f, " >> %d;\n", cell->parameters.at("\\OFFSET").as_int());
+ return true;
+ }
+
+ if (cell->type == "$concat")
+ {
+ fprintf(f, "%s" "assign ", indent.c_str());
+ dump_sigspec(f, cell->connections["\\Y"]);
+ fprintf(f, " = { ");
+ dump_sigspec(f, cell->connections["\\B"]);
+ fprintf(f, " , ");
+ dump_sigspec(f, cell->connections["\\A"]);
+ fprintf(f, " };\n");
+ return true;
+ }
+
if (cell->type == "$dff" || cell->type == "$adff")
{
RTLIL::SigSpec sig_clk, sig_arst, val_arst;
diff --git a/kernel/celltypes.h b/kernel/celltypes.h
index 9e63e9d1..24504aee 100644
--- a/kernel/celltypes.h
+++ b/kernel/celltypes.h
@@ -270,6 +270,20 @@ struct CellTypes
static RTLIL::Const eval(RTLIL::Cell *cell, const RTLIL::Const &arg1, const RTLIL::Const &arg2)
{
+ if (cell->type == "$slice") {
+ RTLIL::Const ret;
+ int width = cell->parameters.at("\\Y_WIDTH").as_int();
+ int offset = cell->parameters.at("\\OFFSET").as_int();
+ ret.bits.insert(ret.bits.end(), arg1.bits.begin()+offset, arg1.bits.begin()+offset+width);
+ return ret;
+ }
+
+ if (cell->type == "$concat") {
+ RTLIL::Const ret = arg1;
+ ret.bits.insert(ret.bits.end(), arg2.bits.begin(), arg2.bits.end());
+ return ret;
+ }
+
bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
@@ -289,10 +303,7 @@ struct CellTypes
}
assert(sel.bits.size() == 0);
- bool signed_a = cell->parameters.count("\\A_SIGNED") > 0 && cell->parameters["\\A_SIGNED"].as_bool();
- bool signed_b = cell->parameters.count("\\B_SIGNED") > 0 && cell->parameters["\\B_SIGNED"].as_bool();
- int result_len = cell->parameters.count("\\Y_WIDTH") > 0 ? cell->parameters["\\Y_WIDTH"].as_int() : -1;
- return eval(cell->type, arg1, arg2, signed_a, signed_b, result_len);
+ return eval(cell, arg1, arg2);
}
};
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 12aa35df..4c944c93 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -462,6 +462,24 @@ namespace {
return;
}
+ if (cell->type == "$slice") {
+ param("\\OFFSET");
+ port("\\A", param("\\A_WIDTH"));
+ port("\\Y", param("\\Y_WIDTH"));
+ if (param("\\OFFSET") + param("\\Y_WIDTH") > param("\\A_WIDTH"))
+ error(__LINE__);
+ check_expected();
+ return;
+ }
+
+ if (cell->type == "$concat") {
+ port("\\A", param("\\A_WIDTH"));
+ port("\\B", param("\\B_WIDTH"));
+ port("\\Y", param("\\A_WIDTH") + param("\\B_WIDTH"));
+ check_expected();
+ return;
+ }
+
if (cell->type == "$mux") {
port("\\A", param("\\WIDTH"));
port("\\B", param("\\WIDTH"));
diff --git a/kernel/satgen.h b/kernel/satgen.h
index 473aa616..840700cb 100644
--- a/kernel/satgen.h
+++ b/kernel/satgen.h
@@ -761,6 +761,27 @@ struct SatGen
return true;
}
+ if (cell->type == "$slice")
+ {
+ RTLIL::SigSpec a = cell->connections.at("\\A");
+ RTLIL::SigSpec y = cell->connections.at("\\Y");
+ ez->assume(signals_eq(a.extract(cell->parameters.at("\\OFFSET").as_int(), y.width), y, timestep));
+ return true;
+ }
+
+ if (cell->type == "$concat")
+ {
+ RTLIL::SigSpec a = cell->connections.at("\\A");
+ RTLIL::SigSpec b = cell->connections.at("\\B");
+ RTLIL::SigSpec y = cell->connections.at("\\Y");
+
+ RTLIL::SigSpec ab = a;
+ ab.append(b);
+
+ ez->assume(signals_eq(ab, y, timestep));
+ return true;
+ }
+
if (timestep > 0 && (cell->type == "$dff" || cell->type == "$_DFF_N_" || cell->type == "$_DFF_P_"))
{
if (timestep == 1)
diff --git a/manual/CHAPTER_CellLib.tex b/manual/CHAPTER_CellLib.tex
index c8c2b6c6..e7895521 100644
--- a/manual/CHAPTER_CellLib.tex
+++ b/manual/CHAPTER_CellLib.tex
@@ -429,3 +429,7 @@ using the {\tt abc} pass.
Add information about {\tt \$assert} cells.
\end{fixme}
+\begin{fixme}
+Add information about {\tt \$slice} and {\tt \$concat} cells.
+\end{fixme}
+
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index e06a80bb..e67b1e05 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -312,6 +312,22 @@ static void simplemap_mux(RTLIL::Module *module, RTLIL::Cell *cell)
}
}
+static void simplemap_slice(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ int offset = cell->parameters.at("\\OFFSET").as_int();
+ RTLIL::SigSpec sig_a = cell->connections.at("\\A");
+ RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
+ module->connections.push_back(RTLIL::SigSig(sig_y, sig_a.extract(offset, sig_y.width)));
+}
+
+static void simplemap_concat(RTLIL::Module *module, RTLIL::Cell *cell)
+{
+ RTLIL::SigSpec sig_ab = cell->connections.at("\\A");
+ sig_ab.append(cell->connections.at("\\B"));
+ RTLIL::SigSpec sig_y = cell->connections.at("\\Y");
+ module->connections.push_back(RTLIL::SigSig(sig_y, sig_ab));
+}
+
static void simplemap_sr(RTLIL::Module *module, RTLIL::Cell *cell)
{
int width = cell->parameters.at("\\WIDTH").as_int();
@@ -480,6 +496,8 @@ void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::
mappers["$logic_and"] = simplemap_logbin;
mappers["$logic_or"] = simplemap_logbin;
mappers["$mux"] = simplemap_mux;
+ mappers["$slice"] = simplemap_slice;
+ mappers["$concat"] = simplemap_concat;
mappers["$sr"] = simplemap_sr;
mappers["$dff"] = simplemap_dff;
mappers["$dffsr"] = simplemap_dffsr;
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 87e83bd1..4436abfe 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -829,6 +829,36 @@ endmodule
// --------------------------------------------------------
+module \$slice (A, Y);
+
+parameter OFFSET = 0;
+parameter A_WIDTH = 0;
+parameter Y_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+output [Y_WIDTH-1:0] Y;
+
+assign Y = A >> OFFSET;
+
+endmodule
+
+// --------------------------------------------------------
+
+module \$concat (A, B, Y);
+
+parameter A_WIDTH = 0;
+parameter B_WIDTH = 0;
+
+input [A_WIDTH-1:0] A;
+input [B_WIDTH-1:0] B;
+output [A_WIDTH+B_WIDTH-1:0] Y;
+
+assign Y = {B, A};
+
+endmodule
+
+// --------------------------------------------------------
+
module \$mux (A, B, S, Y);
parameter WIDTH = 0;
diff --git a/techlibs/common/stdcells.v b/techlibs/common/stdcells.v
index e33e651c..fdee26b6 100644
--- a/techlibs/common/stdcells.v
+++ b/techlibs/common/stdcells.v
@@ -957,6 +957,18 @@ endmodule
// --------------------------------------------------------
(* techmap_simplemap *)
+module \$slice ;
+endmodule
+
+// --------------------------------------------------------
+
+(* techmap_simplemap *)
+module \$concat ;
+endmodule
+
+// --------------------------------------------------------
+
+(* techmap_simplemap *)
module \$mux ;
endmodule
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-26 02:57:52 +0000