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-rw-r--r--kernel/cost.h84
-rw-r--r--passes/abc/abc.cc31
2 files changed, 100 insertions, 15 deletions
diff --git a/kernel/cost.h b/kernel/cost.h
new file mode 100644
index 00000000..17aca837
--- /dev/null
+++ b/kernel/cost.h
@@ -0,0 +1,84 @@
+/*
+ * yosys -- Yosys Open SYnthesis Suite
+ *
+ * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
+ *
+ * Permission to use, copy, modify, and/or distribute this software for any
+ * purpose with or without fee is hereby granted, provided that the above
+ * copyright notice and this permission notice appear in all copies.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
+ * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
+ * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
+ * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
+ * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
+ * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
+ *
+ */
+
+#ifndef COST_H
+#define COST_H
+
+#include <kernel/yosys.h>
+
+YOSYS_NAMESPACE_BEGIN
+
+int get_cell_cost(RTLIL::Cell *cell, std::map<RTLIL::Module*, int> *mod_cost_cache = nullptr);
+
+int get_cell_cost(RTLIL::IdString type, const std::map<RTLIL::IdString, RTLIL::Const> &parameters = std::map<RTLIL::IdString, RTLIL::Const>(),
+ RTLIL::Design *design = nullptr, std::map<RTLIL::Module*, int> *mod_cost_cache = nullptr)
+{
+ static std::map<RTLIL::IdString, int> gate_cost = {
+ { "$_BUF_", 1 },
+ { "$_NOT_", 2 },
+ { "$_AND_", 4 },
+ { "$_NAND_", 4 },
+ { "$_OR_", 4 },
+ { "$_NOR_", 4 },
+ { "$_XOR_", 8 },
+ { "$_XNOR_", 8 },
+ { "$_AOI3_", 6 },
+ { "$_OAI3_", 6 },
+ { "$_AOI4_", 8 },
+ { "$_OAI4_", 8 },
+ { "$_MUX_", 4 }
+ };
+
+ if (gate_cost.count(type))
+ return gate_cost.at(type);
+
+ if (parameters.empty() && design && design->module(type))
+ {
+ RTLIL::Module *mod = design->module(type);
+
+ if (mod->attributes.count("\\cost"))
+ return mod->attributes.at("\\cost").as_int();
+
+ std::map<RTLIL::Module*, int> local_mod_cost_cache;
+ if (mod_cost_cache == nullptr)
+ mod_cost_cache = &local_mod_cost_cache;
+
+ if (mod_cost_cache->count(mod))
+ return mod_cost_cache->at(mod);
+
+ int module_cost = 1;
+ for (auto c : mod->cells())
+ module_cost += get_cell_cost(c, mod_cost_cache);
+
+ (*mod_cost_cache)[mod] = module_cost;
+ return module_cost;
+ }
+
+ log("Warning: Can't determine cost of %s cell (%d parameters).\n", log_id(type), SIZE(parameters));
+ return 1;
+}
+
+int get_cell_cost(RTLIL::Cell *cell, std::map<RTLIL::Module*, int> *mod_cost_cache)
+{
+ return get_cell_cost(cell->type, cell->parameters, cell->module->design, mod_cost_cache);
+}
+
+YOSYS_NAMESPACE_END
+
+#endif
diff --git a/passes/abc/abc.cc b/passes/abc/abc.cc
index 3e105411..48789494 100644
--- a/passes/abc/abc.cc
+++ b/passes/abc/abc.cc
@@ -41,6 +41,7 @@
#include "kernel/register.h"
#include "kernel/sigtools.h"
+#include "kernel/cost.h"
#include "kernel/log.h"
#include <unistd.h>
#include <stdlib.h>
@@ -719,21 +720,21 @@ static void abc_module(RTLIL::Design *design, RTLIL::Module *current_module, std
f = fopen(p, "wt");
if (f == NULL)
log_error("Opening %s for writing failed: %s\n", p, strerror(errno));
- fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
- fprintf(f, "GATE ONE 1 Y=CONST1;\n");
- fprintf(f, "GATE BUF 1 Y=A; PIN * NONINV 1 999 1 0 1 0\n");
- fprintf(f, "GATE NOT 1 Y=!A; PIN * INV 1 999 1 0 1 0\n");
- fprintf(f, "GATE AND 1 Y=A*B; PIN * NONINV 1 999 1 0 1 0\n");
- fprintf(f, "GATE NAND 1 Y=!(A*B); PIN * INV 1 999 1 0 1 0\n");
- fprintf(f, "GATE OR 1 Y=A+B; PIN * NONINV 1 999 1 0 1 0\n");
- fprintf(f, "GATE NOR 1 Y=!(A+B); PIN * INV 1 999 1 0 1 0\n");
- fprintf(f, "GATE XOR 1 Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n");
- fprintf(f, "GATE XNOR 1 Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n");
- fprintf(f, "GATE MUX 1 Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n");
- fprintf(f, "GATE AOI3 1 Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n");
- fprintf(f, "GATE OAI3 1 Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n");
- fprintf(f, "GATE AOI4 1 Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n");
- fprintf(f, "GATE OAI4 1 Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n");
+ fprintf(f, "GATE ZERO 1 Y=CONST0;\n");
+ fprintf(f, "GATE ONE 1 Y=CONST1;\n");
+ fprintf(f, "GATE BUF %d Y=A; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_BUF_"));
+ fprintf(f, "GATE NOT %d Y=!A; PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOT_"));
+ fprintf(f, "GATE AND %d Y=A*B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_AND_"));
+ fprintf(f, "GATE NAND %d Y=!(A*B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NAND_"));
+ fprintf(f, "GATE OR %d Y=A+B; PIN * NONINV 1 999 1 0 1 0\n", get_cell_cost("$_OR_"));
+ fprintf(f, "GATE NOR %d Y=!(A+B); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_NOR_"));
+ fprintf(f, "GATE XOR %d Y=(A*!B)+(!A*B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XOR_"));
+ fprintf(f, "GATE XNOR %d Y=(A*B)+(!A*!B); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_XNOR_"));
+ fprintf(f, "GATE AOI3 %d Y=!((A*B)+C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI3_"));
+ fprintf(f, "GATE OAI3 %d Y=!((A+B)*C); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI3_"));
+ fprintf(f, "GATE AOI4 %d Y=!((A*B)+(C*D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_AOI4_"));
+ fprintf(f, "GATE OAI4 %d Y=!((A+B)*(C+D)); PIN * INV 1 999 1 0 1 0\n", get_cell_cost("$_OAI4_"));
+ fprintf(f, "GATE MUX %d Y=(A*B)+(S*B)+(!S*A); PIN * UNKNOWN 1 999 1 0 1 0\n", get_cell_cost("$_MUX_"));
fclose(f);
free(p);