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Diffstat (limited to 'README')
| -rw-r--r-- | README | 6 |
1 files changed, 3 insertions, 3 deletions
@@ -254,9 +254,9 @@ Verilog Attributes and non-standard features passes to identify input and output ports of cells. The verilog backend also does not output placeholder modules on default. -- The "keep" attribute on cells is used to mark cells that should never be - removed by the optimizer. This is used for example for cells that have - hidden connections that are not part of the netlist, such as IO pads. +- The "keep" attribute on cells and wires is used to mark objects that should + never be removed by the optimizer. This is used for example for cells that + have hidden connections that are not part of the netlist, such as IO pads. - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes |