diff options
Diffstat (limited to 'README')
| -rw-r--r-- | README | 6 |
1 files changed, 6 insertions, 0 deletions
@@ -205,6 +205,12 @@ Verilog Attributes and non-standard features temporary variable within an always block. This is mostly used internally by yosys to synthesize verilog functions and access arrays. +- The "placeholder" attribute on modules is used to mark empty stub modules + that have the same ports as the real thing but do not contain information + on the internal configuration. This modules are only used by the synthesis + passes to identify input and output ports of cells. The verilog backend + also does not output placeholder modules on default. + - In addition to the (* ... *) attribute syntax, yosys supports the non-standard {* ... *} attribute syntax to set default attributes for everything that comes after the {* ... *} statement. (Reset |