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-rw-r--r--backends/autotest/autotest.cc5
1 files changed, 2 insertions, 3 deletions
diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc
index 028d1f37..db49880a 100644
--- a/backends/autotest/autotest.cc
+++ b/backends/autotest/autotest.cc
@@ -119,10 +119,9 @@ static void autotest(FILE *f, RTLIL::Design *design)
if ((*it4)->type == RTLIL::ST0 || (*it4)->type == RTLIL::ST1)
continue;
RTLIL::SigSpec &signal = (*it4)->signal;
- for (size_t i = 0; i < signal.chunks().size(); i++) {
- if (signal.chunks()[i].wire == wire)
+ for (auto &c : signal.chunks())
+ if (c.wire == wire)
is_clksignal = true;
- }
}
if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
signal_clk[idy("sig", mod->name, wire->name)] = wire->width;