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-rw-r--r--backends/spice/spice.cc2
1 files changed, 1 insertions, 1 deletions
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index 390822ed..2c614178 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -84,7 +84,7 @@ static void print_spice_module(std::ostream &f, RTLIL::Module *module, RTLIL::De
RTLIL::SigSpec sig(RTLIL::State::Sz, wire->width);
if (cell->hasPort(wire->name)) {
sig = sigmap(cell->getPort(wire->name));
- sig.extend(wire->width, false);
+ sig.extend_u0(wire->width, false);
}
port_sigs.push_back(sig);
}