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-rw-r--r--backends/verilog/verilog_backend.cc3
1 files changed, 2 insertions, 1 deletions
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 82a2c519..bbdbbbfa 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -973,7 +973,8 @@ void dump_module(std::ostream &f, std::string indent, RTLIL::Module *module)
for (int i = 0; i < wire->width; i++)
if (reg_bits.count(std::pair<RTLIL::Wire*,int>(wire, i)) == 0)
goto this_wire_aint_reg;
- reg_wires.insert(wire->name);
+ if (wire->width)
+ reg_wires.insert(wire->name);
this_wire_aint_reg:;
}
}