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-rw-r--r--backends/autotest/autotest.cc4
-rw-r--r--backends/blif/blif.cc8
-rw-r--r--backends/btor/btor.cc4
-rw-r--r--backends/edif/edif.cc12
-rw-r--r--backends/ilang/ilang_backend.cc4
-rw-r--r--backends/intersynth/intersynth.cc2
-rw-r--r--backends/spice/spice.cc8
-rw-r--r--backends/verilog/verilog_backend.cc2
8 files changed, 22 insertions, 22 deletions
diff --git a/backends/autotest/autotest.cc b/backends/autotest/autotest.cc
index 06b2c2a9..3bb0f9d6 100644
--- a/backends/autotest/autotest.cc
+++ b/backends/autotest/autotest.cc
@@ -91,7 +91,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
fprintf(f, "end\n");
fprintf(f, "endtask\n\n");
- for (auto it = design->modules.begin(); it != design->modules.end(); it++)
+ for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
{
std::map<std::string, int> signal_in;
std::map<std::string, std::string> signal_const;
@@ -292,7 +292,7 @@ static void autotest(FILE *f, RTLIL::Design *design)
fprintf(f, "initial begin\n");
fprintf(f, "\t// $dumpfile(\"testbench.vcd\");\n");
fprintf(f, "\t// $dumpvars(0, testbench);\n");
- for (auto it = design->modules.begin(); it != design->modules.end(); it++)
+ for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
if (!it->second->get_bool_attribute("\\gentb_skip"))
fprintf(f, "\t%s;\n", idy(it->first, "test").c_str());
fprintf(f, "\t$finish;\n");
diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index 936dea02..2b783e73 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -89,9 +89,9 @@ struct BlifDumper
{
if (!config->gates_mode)
return "subckt";
- if (!design->modules.count(RTLIL::escape_id(cell_type)))
+ if (!design->modules_.count(RTLIL::escape_id(cell_type)))
return "gate";
- if (design->modules.at(RTLIL::escape_id(cell_type))->get_bool_attribute("\\blackbox"))
+ if (design->modules_.at(RTLIL::escape_id(cell_type))->get_bool_attribute("\\blackbox"))
return "gate";
return "subckt";
}
@@ -362,7 +362,7 @@ struct BlifBackend : public Backend {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules)
+ for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first;
@@ -370,7 +370,7 @@ struct BlifBackend : public Backend {
std::vector<RTLIL::Module*> mod_list;
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index ef0f0dd8..4af12100 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -964,7 +964,7 @@ struct BtorBackend : public Backend {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules)
+ for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first;
@@ -975,7 +975,7 @@ struct BtorBackend : public Backend {
std::vector<RTLIL::Module*> mod_list;
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index d23e99e7..5eff4598 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -125,11 +125,11 @@ struct EdifBackend : public Backend {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules)
+ for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first;
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))
@@ -146,7 +146,7 @@ struct EdifBackend : public Backend {
for (auto cell_it : module->cells_)
{
RTLIL::Cell *cell = cell_it.second;
- if (!design->modules.count(cell->type) || design->modules.at(cell->type)->get_bool_attribute("\\blackbox")) {
+ if (!design->modules_.count(cell->type) || design->modules_.at(cell->type)->get_bool_attribute("\\blackbox")) {
lib_cell_ports[cell->type];
for (auto p : cell->connections()) {
if (p.second.size() > 1)
@@ -213,11 +213,11 @@ struct EdifBackend : public Backend {
// extract module dependencies
std::map<RTLIL::Module*, std::set<RTLIL::Module*>> module_deps;
- for (auto &mod_it : design->modules) {
+ for (auto &mod_it : design->modules_) {
module_deps[mod_it.second] = std::set<RTLIL::Module*>();
for (auto &cell_it : mod_it.second->cells_)
- if (design->modules.count(cell_it.second->type) > 0)
- module_deps[mod_it.second].insert(design->modules.at(cell_it.second->type));
+ if (design->modules_.count(cell_it.second->type) > 0)
+ module_deps[mod_it.second].insert(design->modules_.at(cell_it.second->type));
}
// simple good-enough topological sort
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index be4e2777..d45e94a0 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -339,7 +339,7 @@ void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design, bool only_
if (!flag_m) {
int count_selected_mods = 0;
- for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
+ for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
if (design->selected_whole_module(it->first))
flag_m = true;
if (design->selected(it->second))
@@ -355,7 +355,7 @@ void ILANG_BACKEND::dump_design(FILE *f, const RTLIL::Design *design, bool only_
fprintf(f, "autoidx %d\n", RTLIL::autoidx);
}
- for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
+ for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
if (!only_selected || design->selected(it->second)) {
if (only_selected)
fprintf(f, "\n");
diff --git a/backends/intersynth/intersynth.cc b/backends/intersynth/intersynth.cc
index a463f5ec..2f94e290 100644
--- a/backends/intersynth/intersynth.cc
+++ b/backends/intersynth/intersynth.cc
@@ -121,7 +121,7 @@ struct IntersynthBackend : public Backend {
for (auto lib : libs)
ct.setup_design(lib);
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
SigMap sigmap(module);
diff --git a/backends/spice/spice.cc b/backends/spice/spice.cc
index c58e4bec..283448c3 100644
--- a/backends/spice/spice.cc
+++ b/backends/spice/spice.cc
@@ -54,7 +54,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
std::vector<RTLIL::SigSpec> port_sigs;
- if (design->modules.count(cell->type) == 0)
+ if (design->modules_.count(cell->type) == 0)
{
log("Warning: no (blackbox) module for cell type `%s' (%s.%s) found! Guessing order of ports.\n",
RTLIL::id2cstr(cell->type), RTLIL::id2cstr(module->name), RTLIL::id2cstr(cell->name));
@@ -65,7 +65,7 @@ static void print_spice_module(FILE *f, RTLIL::Module *module, RTLIL::Design *de
}
else
{
- RTLIL::Module *mod = design->modules.at(cell->type);
+ RTLIL::Module *mod = design->modules_.at(cell->type);
std::vector<RTLIL::Wire*> ports;
for (auto wire_it : mod->wires_) {
@@ -171,14 +171,14 @@ struct SpiceBackend : public Backend {
extra_args(f, filename, args, argidx);
if (top_module_name.empty())
- for (auto & mod_it:design->modules)
+ for (auto & mod_it:design->modules_)
if (mod_it.second->get_bool_attribute("\\top"))
top_module_name = mod_it.first;
fprintf(f, "* SPICE netlist generated by %s\n", yosys_version_str);
fprintf(f, "\n");
- for (auto module_it : design->modules)
+ for (auto module_it : design->modules_)
{
RTLIL::Module *module = module_it.second;
if (module->get_bool_attribute("\\blackbox"))
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 098e29f9..f7f0ecaf 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1055,7 +1055,7 @@ struct VerilogBackend : public Backend {
extra_args(f, filename, args, argidx);
fprintf(f, "/* Generated by %s */\n", yosys_version_str);
- for (auto it = design->modules.begin(); it != design->modules.end(); it++) {
+ for (auto it = design->modules_.begin(); it != design->modules_.end(); it++) {
if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
continue;
if (selected && !design->selected_whole_module(it->first)) {