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-rw-r--r--backends/ilang/ilang_backend.cc74
-rw-r--r--backends/verilog/verilog_backend.cc2
2 files changed, 26 insertions, 50 deletions
diff --git a/backends/ilang/ilang_backend.cc b/backends/ilang/ilang_backend.cc
index 60fb0990..6a697413 100644
--- a/backends/ilang/ilang_backend.cc
+++ b/backends/ilang/ilang_backend.cc
@@ -113,11 +113,9 @@ void ILANG_BACKEND::dump_sigspec(std::ostream &f, const RTLIL::SigSpec &sig, boo
void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::Wire *wire)
{
- std::map<RTLIL::IdString, RTLIL::Const, RTLIL::sort_by_id_str> sorted_attributes(wire->attributes.begin(), wire->attributes.end());
-
- for (auto it = sorted_attributes.begin(); it != sorted_attributes.end(); ++it) {
- f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
- dump_const(f, it->second);
+ for (auto &it : wire->attributes) {
+ f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
+ dump_const(f, it.second);
f << stringf("\n");
}
f << stringf("%s" "wire ", indent.c_str());
@@ -138,11 +136,9 @@ void ILANG_BACKEND::dump_wire(std::ostream &f, std::string indent, const RTLIL::
void ILANG_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL::Memory *memory)
{
- std::map<RTLIL::IdString, RTLIL::Const, RTLIL::sort_by_id_str> sorted_attributes(memory->attributes.begin(), memory->attributes.end());
-
- for (auto it = sorted_attributes.begin(); it != sorted_attributes.end(); ++it) {
- f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
- dump_const(f, it->second);
+ for (auto &it : memory->attributes) {
+ f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
+ dump_const(f, it.second);
f << stringf("\n");
}
f << stringf("%s" "memory ", indent.c_str());
@@ -157,24 +153,20 @@ void ILANG_BACKEND::dump_memory(std::ostream &f, std::string indent, const RTLIL
void ILANG_BACKEND::dump_cell(std::ostream &f, std::string indent, const RTLIL::Cell *cell)
{
- std::map<RTLIL::IdString, RTLIL::Const, RTLIL::sort_by_id_str> sorted_attributes(cell->attributes.begin(), cell->attributes.end());
- std::map<RTLIL::IdString, RTLIL::Const, RTLIL::sort_by_id_str> sorted_parameters(cell->parameters.begin(), cell->parameters.end());
- std::map<RTLIL::IdString, RTLIL::SigSpec, RTLIL::sort_by_id_str> sorted_connections(cell->connections().begin(), cell->connections().end());
-
- for (auto it = sorted_attributes.begin(); it != sorted_attributes.end(); ++it) {
- f << stringf("%s" "attribute %s ", indent.c_str(), it->first.c_str());
- dump_const(f, it->second);
+ for (auto &it : cell->attributes) {
+ f << stringf("%s" "attribute %s ", indent.c_str(), it.first.c_str());
+ dump_const(f, it.second);
f << stringf("\n");
}
f << stringf("%s" "cell %s %s\n", indent.c_str(), cell->type.c_str(), cell->name.c_str());
- for (auto it = sorted_parameters.begin(); it != sorted_parameters.end(); ++it) {
- f << stringf("%s parameter%s %s ", indent.c_str(), (it->second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", it->first.c_str());
- dump_const(f, it->second);
+ for (auto &it : cell->parameters) {
+ f << stringf("%s parameter%s %s ", indent.c_str(), (it.second.flags & RTLIL::CONST_FLAG_SIGNED) != 0 ? " signed" : "", it.first.c_str());
+ dump_const(f, it.second);
f << stringf("\n");
}
- for (auto it = sorted_connections.begin(); it != sorted_connections.end(); ++it) {
- f << stringf("%s connect %s ", indent.c_str(), it->first.c_str());
- dump_sigspec(f, it->second);
+ for (auto &it : cell->connections()) {
+ f << stringf("%s connect %s ", indent.c_str(), it.first.c_str());
+ dump_sigspec(f, it.second);
f << stringf("\n");
}
f << stringf("%s" "end\n", indent.c_str());
@@ -289,52 +281,32 @@ void ILANG_BACKEND::dump_module(std::ostream &f, std::string indent, RTLIL::Modu
if (print_body)
{
- std::vector<RTLIL::Wire*> sorted_wires;
for (auto it : module->wires())
- sorted_wires.push_back(it);
- std::sort(sorted_wires.begin(), sorted_wires.end(), RTLIL::sort_by_name_str<RTLIL::Wire>());
-
- std::vector<RTLIL::Memory*> sorted_memories;
- for (auto it : module->memories)
- sorted_memories.push_back(it.second);
- std::sort(sorted_memories.begin(), sorted_memories.end(), RTLIL::sort_by_name_str<RTLIL::Memory>());
-
- std::vector<RTLIL::Cell*> sorted_cells;
- for (auto it : module->cells())
- sorted_cells.push_back(it);
- std::sort(sorted_cells.begin(), sorted_cells.end(), RTLIL::sort_by_name_str<RTLIL::Cell>());
-
- std::vector<RTLIL::Process*> sorted_processes;
- for (auto it : module->processes)
- sorted_processes.push_back(it.second);
- std::sort(sorted_processes.begin(), sorted_processes.end(), RTLIL::sort_by_name_str<RTLIL::Process>());
-
- for (auto it : sorted_wires)
if (!only_selected || design->selected(module, it)) {
if (only_selected)
f << stringf("\n");
dump_wire(f, indent + " ", it);
}
- for (auto it : sorted_memories)
- if (!only_selected || design->selected(module, it)) {
+ for (auto it : module->memories)
+ if (!only_selected || design->selected(module, it.second)) {
if (only_selected)
f << stringf("\n");
- dump_memory(f, indent + " ", it);
+ dump_memory(f, indent + " ", it.second);
}
- for (auto it : sorted_cells)
+ for (auto it : module->cells())
if (!only_selected || design->selected(module, it)) {
if (only_selected)
f << stringf("\n");
dump_cell(f, indent + " ", it);
}
- for (auto it : sorted_processes)
- if (!only_selected || design->selected(module, it)) {
+ for (auto it : module->processes)
+ if (!only_selected || design->selected(module, it.second)) {
if (only_selected)
f << stringf("\n");
- dump_proc(f, indent + " ", it);
+ dump_proc(f, indent + " ", it.second);
}
bool first_conn_line = true;
@@ -430,6 +402,8 @@ struct IlangBackend : public Backend {
}
extra_args(f, filename, args, argidx);
+ design->sort();
+
log("Output filename: %s\n", filename.c_str());
*f << stringf("# Generated by %s\n", yosys_version_str);
ILANG_BACKEND::dump_design(*f, design, selected, true, false);
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index e9f4691b..ab0844d7 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -1137,6 +1137,8 @@ struct VerilogBackend : public Backend {
}
extra_args(f, filename, args, argidx);
+ design->sort();
+
*f << stringf("/* Generated by %s */\n", yosys_version_str);
for (auto it = design->modules_.begin(); it != design->modules_.end(); ++it) {
if (it->second->get_bool_attribute("\\blackbox") != blackboxes)
generated by cgit v1.2.3 (git 2.25.1) at 2024-04-24 22:02:30 +0000