diff options
Diffstat (limited to 'backends')
| -rw-r--r-- | backends/edif/edif.cc | 2 | ||||
| -rw-r--r-- | backends/verilog/verilog_backend.cc | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc index 7f29cd41..15b562ca 100644 --- a/backends/edif/edif.cc +++ b/backends/edif/edif.cc @@ -308,7 +308,7 @@ struct EdifBackend : public Backend { *f << stringf(")\n"); for (auto &p : cell->connections()) { RTLIL::SigSpec sig = sigmap(p.second); - for (int i = 0; i < SIZE(sig); i++) + for (int i = 0; i < GetSize(sig); i++) if (sig.size() == 1) net_join_db[sig[i]].insert(stringf("(portRef %s (instanceRef %s))", EDIF_REF(p.first), EDIF_REF(cell->name))); else diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 99430d04..814c87be 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -315,7 +315,7 @@ std::string cellname(RTLIL::Cell *cell) if (!norename && cell->name[0] == '$' && reg_ct.count(cell->type) && cell->hasPort("\\Q")) { RTLIL::SigSpec sig = cell->getPort("\\Q"); - if (SIZE(sig) != 1 || sig.is_fully_const()) + if (GetSize(sig) != 1 || sig.is_fully_const()) goto no_special_reg_name; RTLIL::Wire *wire = sig[0].wire; |