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-rw-r--r--backends/btor/btor.cc8
-rw-r--r--backends/verilog/verilog_backend.cc8
2 files changed, 8 insertions, 8 deletions
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index 0316f7ab..bbfbc0f9 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -193,7 +193,7 @@ struct BtorDumper
break;
log(" -- found cell %s\n", cstr(cell_id));
RTLIL::Cell* cell = module->cells.at(cell_id);
- RTLIL::SigSpec* cell_output = get_cell_output(cell);
+ const RTLIL::SigSpec* cell_output = get_cell_output(cell);
int cell_line = dump_cell(cell);
if(dep_set.size()==1 && wire->width == cell_output->size())
@@ -796,9 +796,9 @@ struct BtorDumper
}
}
- RTLIL::SigSpec* get_cell_output(RTLIL::Cell* cell)
+ const RTLIL::SigSpec* get_cell_output(RTLIL::Cell* cell)
{
- RTLIL::SigSpec *output_sig = nullptr;
+ const RTLIL::SigSpec *output_sig = nullptr;
if (cell->type == "$memrd")
{
output_sig = &cell->connections().at(RTLIL::IdString("\\DATA"));
@@ -835,7 +835,7 @@ struct BtorDumper
for (auto it = module->cells.begin(); it != module->cells.end(); ++it)
{
RTLIL::Cell *cell = it->second;
- RTLIL::SigSpec* output_sig = get_cell_output(cell);
+ const RTLIL::SigSpec* output_sig = get_cell_output(cell);
if(output_sig==nullptr)
continue;
RTLIL::SigSpec s = sigmap(*output_sig);
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index aa2f88fa..6bef90e3 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -223,7 +223,7 @@ void dump_sigchunk(FILE *f, const RTLIL::SigChunk &chunk, bool no_decimal = fals
}
}
-void dump_sigspec(FILE *f, RTLIL::SigSpec &sig)
+void dump_sigspec(FILE *f, const RTLIL::SigSpec &sig)
{
if (sig.is_chunk()) {
dump_sigchunk(f, sig.as_chunk());
@@ -293,10 +293,10 @@ void dump_cell_expr_port(FILE *f, RTLIL::Cell *cell, std::string port, bool gen_
{
if (gen_signed && cell->parameters.count("\\" + port + "_SIGNED") > 0 && cell->parameters["\\" + port + "_SIGNED"].as_bool()) {
fprintf(f, "$signed(");
- dump_sigspec(f, cell->connections()["\\" + port]);
+ dump_sigspec(f, cell->get("\\" + port));
fprintf(f, ")");
} else
- dump_sigspec(f, cell->connections()["\\" + port]);
+ dump_sigspec(f, cell->get("\\" + port));
}
std::string cellname(RTLIL::Cell *cell)
@@ -735,7 +735,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell)
fprintf(f, "\n%s" ");\n", indent.c_str());
}
-void dump_conn(FILE *f, std::string indent, RTLIL::SigSpec &left, RTLIL::SigSpec &right)
+void dump_conn(FILE *f, std::string indent, const RTLIL::SigSpec &left, const RTLIL::SigSpec &right)
{
fprintf(f, "%s" "assign ", indent.c_str());
dump_sigspec(f, left);