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-rw-r--r--debian/control5
1 files changed, 3 insertions, 2 deletions
diff --git a/debian/control b/debian/control
index 1ef00dd3..9f5ee53a 100644
--- a/debian/control
+++ b/debian/control
@@ -14,6 +14,7 @@ Build-Depends: debhelper (>= 9),
libffi-dev,
pkg-config,
txt2man,
+ iverilog (>= 10.1),
python3
Build-Depends-Indep:
texlive-base,
@@ -28,7 +29,7 @@ Build-Depends-Indep:
texlive-bibtex-extra,
lmodern,
graphviz,
- berkeley-abc (>= 1.01)
+ berkeley-abc (>= 1.01+20161002hgeb6eca6+dfsg)
Standards-Version: 3.9.8
Vcs-Browser: https://anonscm.debian.org/cgit/debian-science/packages/yosys.git
Vcs-Git: https://anonscm.debian.org/git/debian-science/packages/yosys.git
@@ -39,7 +40,7 @@ Architecture: any
Depends: ${shlibs:Depends},
${python3:Depends},
${misc:Depends},
- berkeley-abc (>= 1.01),
+ berkeley-abc (>= 1.01+20161002hgeb6eca6+dfsg),
xdot
Description: Framework for Verilog RTL synthesis
This is a framework for Verilog RTL synthesis. It currently has extensive