diff options
Diffstat (limited to 'examples/cmos')
| -rw-r--r-- | examples/cmos/counter.ys | 10 | ||||
| -rw-r--r-- | examples/cmos/counter_tb.v | 4 | ||||
| -rw-r--r-- | examples/cmos/testbench_digital.sh | 2 |
3 files changed, 8 insertions, 8 deletions
diff --git a/examples/cmos/counter.ys b/examples/cmos/counter.ys index a784f346..d0b09366 100644 --- a/examples/cmos/counter.ys +++ b/examples/cmos/counter.ys @@ -1,11 +1,12 @@ - read_verilog counter.v read_verilog -lib cmos_cells.v -proc;; memory;; techmap;; - +synth dfflibmap -liberty cmos_cells.lib -abc -liberty cmos_cells.lib;; +abc -liberty cmos_cells.lib +opt_clean + +stat -liberty cmos_cells.lib # http://vlsiarch.ecen.okstate.edu/flows/MOSIS_SCMOS/latest/cadence/lib/tsmc025/signalstorm/osu025_stdcells.lib # dfflibmap -liberty osu025_stdcells.lib @@ -13,4 +14,3 @@ abc -liberty cmos_cells.lib;; write_verilog synth.v write_spice synth.sp - diff --git a/examples/cmos/counter_tb.v b/examples/cmos/counter_tb.v index bcd7d992..11e82507 100644 --- a/examples/cmos/counter_tb.v +++ b/examples/cmos/counter_tb.v @@ -12,7 +12,7 @@ module counter_tb; # 4 reset = 0; # 6 $finish; end - + /* Make enable with period of 8 and 6,7 low */ reg en = 1; always begin @@ -25,7 +25,7 @@ module counter_tb; /* Make a regular pulsing clock. */ reg clk = 0; always #1 clk = !clk; - + /* UUT */ wire [2:0] count; counter c1 (clk, reset, en, count); diff --git a/examples/cmos/testbench_digital.sh b/examples/cmos/testbench_digital.sh index afaaf4d4..d7ab0fe1 100644 --- a/examples/cmos/testbench_digital.sh +++ b/examples/cmos/testbench_digital.sh @@ -4,7 +4,7 @@ set -ex # iverlog simulation echo "Doing Verilog simulation with iverilog" -iverilog -o counter_tb counter.v counter_tb.v +iverilog -o counter_tb counter.v counter_tb.v ./counter_tb; gtkwave counter_tb.gtkw & # yosys synthesis |