summaryrefslogtreecommitdiff
path: root/examples/igloo2
diff options
context:
space:
mode:
Diffstat (limited to 'examples/igloo2')
-rw-r--r--examples/igloo2/.gitignore4
-rw-r--r--examples/igloo2/example.pdc20
-rw-r--r--examples/igloo2/example.sdc2
-rw-r--r--examples/igloo2/example.v64
-rw-r--r--examples/igloo2/libero.tcl57
-rw-r--r--examples/igloo2/runme.sh6
6 files changed, 153 insertions, 0 deletions
diff --git a/examples/igloo2/.gitignore b/examples/igloo2/.gitignore
new file mode 100644
index 00000000..33b7182d
--- /dev/null
+++ b/examples/igloo2/.gitignore
@@ -0,0 +1,4 @@
+/netlist.edn
+/netlist.vm
+/example.stp
+/proj
diff --git a/examples/igloo2/example.pdc b/examples/igloo2/example.pdc
new file mode 100644
index 00000000..298d9e93
--- /dev/null
+++ b/examples/igloo2/example.pdc
@@ -0,0 +1,20 @@
+# Add placement constraints here
+
+set_io clk -pinname H16 -fixed yes -DIRECTION INPUT
+
+set_io SW1 -pinname H12 -fixed yes -DIRECTION INPUT
+set_io SW2 -pinname H13 -fixed yes -DIRECTION INPUT
+
+set_io LED1 -pinname J16 -fixed yes -DIRECTION OUTPUT
+set_io LED2 -pinname M16 -fixed yes -DIRECTION OUTPUT
+set_io LED3 -pinname K16 -fixed yes -DIRECTION OUTPUT
+set_io LED4 -pinname N16 -fixed yes -DIRECTION OUTPUT
+
+set_io AA -pinname L12 -fixed yes -DIRECTION OUTPUT
+set_io AB -pinname L13 -fixed yes -DIRECTION OUTPUT
+set_io AC -pinname M13 -fixed yes -DIRECTION OUTPUT
+set_io AD -pinname N15 -fixed yes -DIRECTION OUTPUT
+set_io AE -pinname L11 -fixed yes -DIRECTION OUTPUT
+set_io AF -pinname L14 -fixed yes -DIRECTION OUTPUT
+set_io AG -pinname N14 -fixed yes -DIRECTION OUTPUT
+set_io CA -pinname M15 -fixed yes -DIRECTION OUTPUT
diff --git a/examples/igloo2/example.sdc b/examples/igloo2/example.sdc
new file mode 100644
index 00000000..f8b48731
--- /dev/null
+++ b/examples/igloo2/example.sdc
@@ -0,0 +1,2 @@
+# Add timing constraints here
+create_clock -period 10.000 -waveform {0.000 5.000} [get_ports {clk}]
diff --git a/examples/igloo2/example.v b/examples/igloo2/example.v
new file mode 100644
index 00000000..4a9486e5
--- /dev/null
+++ b/examples/igloo2/example.v
@@ -0,0 +1,64 @@
+module example (
+ input clk,
+ input SW1,
+ input SW2,
+ output LED1,
+ output LED2,
+ output LED3,
+ output LED4,
+
+ output AA, AB, AC, AD,
+ output AE, AF, AG, CA
+);
+
+ localparam BITS = 8;
+ localparam LOG2DELAY = 22;
+
+ reg [BITS+LOG2DELAY-1:0] counter = 0;
+ reg [BITS-1:0] outcnt;
+
+ always @(posedge clk) begin
+ counter <= counter + SW1 + SW2 + 1;
+ outcnt <= counter >> LOG2DELAY;
+ end
+
+ assign {LED1, LED2, LED3, LED4} = outcnt ^ (outcnt >> 1);
+
+ // assign CA = counter[10];
+ // seg7enc seg7encinst (
+ // .seg({AA, AB, AC, AD, AE, AF, AG}),
+ // .dat(CA ? outcnt[3:0] : outcnt[7:4])
+ // );
+
+ assign {AA, AB, AC, AD, AE, AF, AG} = ~(7'b 100_0000 >> outcnt[6:4]);
+ assign CA = outcnt[7];
+endmodule
+
+module seg7enc (
+ input [3:0] dat,
+ output [6:0] seg
+);
+ reg [6:0] seg_inv;
+ always @* begin
+ seg_inv = 0;
+ case (dat)
+ 4'h0: seg_inv = 7'b 0111111;
+ 4'h1: seg_inv = 7'b 0000110;
+ 4'h2: seg_inv = 7'b 1011011;
+ 4'h3: seg_inv = 7'b 1001111;
+ 4'h4: seg_inv = 7'b 1100110;
+ 4'h5: seg_inv = 7'b 1101101;
+ 4'h6: seg_inv = 7'b 1111101;
+ 4'h7: seg_inv = 7'b 0000111;
+ 4'h8: seg_inv = 7'b 1111111;
+ 4'h9: seg_inv = 7'b 1101111;
+ 4'hA: seg_inv = 7'b 1110111;
+ 4'hB: seg_inv = 7'b 1111100;
+ 4'hC: seg_inv = 7'b 0111001;
+ 4'hD: seg_inv = 7'b 1011110;
+ 4'hE: seg_inv = 7'b 1111001;
+ 4'hF: seg_inv = 7'b 1110001;
+ endcase
+ end
+ assign seg = ~seg_inv;
+endmodule
diff --git a/examples/igloo2/libero.tcl b/examples/igloo2/libero.tcl
new file mode 100644
index 00000000..abc94e47
--- /dev/null
+++ b/examples/igloo2/libero.tcl
@@ -0,0 +1,57 @@
+# Run with "libero SCRIPT:libero.tcl"
+
+file delete -force proj
+
+new_project \
+ -name example \
+ -location proj \
+ -block_mode 0 \
+ -hdl "VERILOG" \
+ -family IGLOO2 \
+ -die PA4MGL2500 \
+ -package vf256 \
+ -speed -1
+
+import_files -hdl_source {netlist.vm}
+import_files -sdc {example.sdc}
+import_files -io_pdc {example.pdc}
+build_design_hierarchy
+set_option -synth 0
+
+organize_tool_files -tool PLACEROUTE \
+ -file {proj/constraint/example.sdc} \
+ -file {proj/constraint/io/example.pdc} \
+ -input_type constraint
+
+organize_tool_files -tool VERIFYTIMING \
+ -file {proj/constraint/example.sdc} \
+ -input_type constraint
+
+configure_tool -name PLACEROUTE \
+ -params TDPR:true \
+ -params PDPR:false \
+ -params EFFORT_LEVEL:false \
+ -params REPAIR_MIN_DELAY:false
+
+puts ""
+puts "**> COMPILE"
+run_tool -name {COMPILE}
+puts "<** COMPILE"
+
+puts ""
+puts "**> PLACEROUTE"
+run_tool -name {PLACEROUTE}
+puts "<** PLACEROUTE"
+
+puts ""
+puts "**> VERIFYTIMING"
+run_tool -name {VERIFYTIMING}
+puts "<** VERIFYTIMING"
+
+puts ""
+puts "**> BITSTREAM"
+export_bitstream_file -trusted_facility_file 1 -trusted_facility_file_components {FABRIC}
+puts "<** BITSTREAM"
+
+puts ""
+exit 0
diff --git a/examples/igloo2/runme.sh b/examples/igloo2/runme.sh
new file mode 100644
index 00000000..a08894e0
--- /dev/null
+++ b/examples/igloo2/runme.sh
@@ -0,0 +1,6 @@
+#!/bin/bash
+set -ex
+yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
+export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost}
+/opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
+cp proj/designer/example/export/example.stp .