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-rw-r--r--frontends/ast/genrtlil.cc3
1 files changed, 0 insertions, 3 deletions
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index 787f4d2d..a2fdcf8b 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -1287,9 +1287,6 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
cell->connections["\\DATA"] = children[1]->genWidthRTLIL(current_module->memories[str]->width);
cell->connections["\\EN"] = children[2]->genRTLIL();
- if (cell->connections["\\EN"].width > 1)
- cell->connections["\\EN"] = uniop2rtlil(this, "$reduce_bool", 1, cell->connections["\\EN"], false);
-
cell->parameters["\\MEMID"] = RTLIL::Const(str);
cell->parameters["\\ABITS"] = RTLIL::Const(addr_bits);
cell->parameters["\\WIDTH"] = RTLIL::Const(current_module->memories[str]->width);