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-rw-r--r--frontends/verilog/preproc.cc6
1 files changed, 3 insertions, 3 deletions
diff --git a/frontends/verilog/preproc.cc b/frontends/verilog/preproc.cc
index e2118630..fb8a7b95 100644
--- a/frontends/verilog/preproc.cc
+++ b/frontends/verilog/preproc.cc
@@ -2,11 +2,11 @@
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
- *
+ *
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
- *
+ *
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
@@ -109,7 +109,7 @@ static std::string next_token(bool pass_newline = false)
}
return token;
}
-
+
if (ch == ' ' || ch == '\t')
{
while ((ch = next_char()) != 0) {