1 files changed, 40 insertions, 3 deletions

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 504f8b3f..0e2bead6 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -145,8 +145,21 @@ struct VerilogFrontend : public Frontend {
 		log("    -nodpi\n");
 		log("        disable DPI-C support\n");
 		log("\n");
+		log("    -noblackbox\n");
+		log("        do not automatically add a (* blackbox *) attribute to an\n");
+		log("        empty module.\n");
+		log("\n");
 		log("    -lib\n");
 		log("        only create empty blackbox modules. This implies -DBLACKBOX.\n");
+		log("        modules with the (* whitebox *) attribute will be preserved.\n");
+		log("        (* lib_whitebox *) will be treated like (* whitebox *).\n");
+		log("\n");
+		log("    -nowb\n");
+		log("        delete (* whitebox *) and (* lib_whitebox *) attributes from\n");
+		log("        all modules.\n");
+		log("\n");
+		log("    -specify\n");
+		log("        parse and import specify blocks\n");
 		log("\n");
 		log("    -noopt\n");
 		log("        don't perform basic optimizations (such as const folding) in the\n");
@@ -155,6 +168,9 @@ struct VerilogFrontend : public Frontend {
 		log("    -icells\n");
 		log("        interpret cell types starting with '$' as internal cell types\n");
 		log("\n");
+		log("    -pwires\n");
+		log("        add a wire for each module parameter\n");
+		log("\n");
 		log("    -nooverwrite\n");
 		log("        ignore re-definitions of modules. (the default behavior is to\n");
 		log("        create an error message if the existing module is not a black box\n");
@@ -215,9 +231,12 @@ struct VerilogFrontend : public Frontend {
 		bool flag_nodpi = false;
 		bool flag_noopt = false;
 		bool flag_icells = false;
+		bool flag_pwires = false;
 		bool flag_nooverwrite = false;
 		bool flag_overwrite = false;
 		bool flag_defer = false;
+		bool flag_noblackbox = false;
+		bool flag_nowb = false;
 		std::map<std::string, std::string> defines_map;
 		std::list<std::string> include_dirs;
 		std::list<std::string> attributes;
@@ -228,10 +247,9 @@ struct VerilogFrontend : public Frontend {
 		norestrict_mode = false;
 		assume_asserts_mode = false;
 		lib_mode = false;
+		specify_mode = false;
 		default_nettype_wire = true;
 
-		log_header(design, "Executing Verilog-2005 frontend.\n");
-
 		args.insert(args.begin()+1, verilog_defaults.begin(), verilog_defaults.end());
 
 		size_t argidx;
@@ -329,11 +347,23 @@ struct VerilogFrontend : public Frontend {
 				flag_nodpi = true;
 				continue;
 			}
+			if (arg == "-noblackbox") {
+				flag_noblackbox = true;
+				continue;
+			}
 			if (arg == "-lib") {
 				lib_mode = true;
 				defines_map["BLACKBOX"] = string();
 				continue;
 			}
+			if (arg == "-nowb") {
+				flag_nowb = true;
+				continue;
+			}
+			if (arg == "-specify") {
+				specify_mode = true;
+				continue;
+			}
 			if (arg == "-noopt") {
 				flag_noopt = true;
 				continue;
@@ -342,6 +372,10 @@ struct VerilogFrontend : public Frontend {
 				flag_icells = true;
 				continue;
 			}
+			if (arg == "-pwires") {
+				flag_pwires = true;
+				continue;
+			}
 			if (arg == "-ignore_redef" || arg == "-nooverwrite") {
 				flag_nooverwrite = true;
 				flag_overwrite = false;
@@ -395,6 +429,8 @@ struct VerilogFrontend : public Frontend {
 		}
 		extra_args(f, filename, args, argidx);
 
+		log_header(design, "Executing Verilog-2005 frontend: %s\n", filename.c_str());
+
 		log("Parsing %s%s input from `%s' to AST representation.\n",
 				formal_mode ? "formal " : "", sv_mode ? "SystemVerilog" : "Verilog", filename.c_str());
 
@@ -429,7 +465,8 @@ struct VerilogFrontend : public Frontend {
 		if (flag_nodpi)
 			error_on_dpi_function(current_ast);
 
-		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
+		AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog1, flag_dump_vlog2, flag_dump_rtlil, flag_nolatches,
+				flag_nomeminit, flag_nomem2reg, flag_mem2reg, flag_noblackbox, lib_mode, flag_nowb, flag_noopt, flag_icells, flag_pwires, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
 
 		if (!flag_nopp)
 			delete lexin;